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IEEE VLSI-TSA International Symposium on VLSI Design
IEEE VLSI-TSA International Symposium on VLSI Design
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1.
Challenge and innovation of VLSI design below 100nm
机译:
VLSI设计的挑战和创新在100nm以下
作者:
Sasaki H.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
VLSI;
innovation management;
integrated circuit design;
integrated circuit manufacture;
nanotechnology;
45 nm;
VLSI design;
architecture innovation;
design field;
design tool;
device characteristics;
manufacturing field;
power dissipation;
process technology;
signal i;
2.
Application specific eFPGAs for SoC platforms
机译:
SoC平台的应用特定EFPGA
作者:
Noll T.G.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit complexity;
circuit optimisation;
digital arithmetic;
embedded systems;
field programmable gate arrays;
integrated circuit design;
logic design;
reconfigurable architectures;
system-on-chip;
SW-programmable kernels;
SoC platforms;
application specific eFPGA;
3.
An RTOS-based approach to design and validation of embedded systems
机译:
基于RTOS的设计和验证嵌入式系统的方法
作者:
Tomiyama H.
;
Chikada S.
;
Honda S.
;
Takada H.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit CAD;
embedded systems;
hardware-software codesign;
integrated circuit design;
microprocessor chips;
RTOS simulation model;
cosimulation framework;
embedded system design;
embedded system validation;
multiprocessor embedded systems;
timing accuracy;
4.
Reconfigurable architectures for network processing
机译:
用于网络处理的可重新配置架构
作者:
Sezer S.
;
McLoone M.
;
McCanny J.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
field programmable gate arrays;
network computers;
quality of service;
reconfigurable architectures;
telecommunication security;
telecommunication traffic;
data encryption/decryption;
network processing;
network security;
network traffic;
node throughput;
packet sc;
5.
Implementation of dynamically reconfigurable processor DAPDNA-2
机译:
实施动态可重构处理器DAPDNA-2
作者:
Sato T.
;
Watanabe H.
;
Shiba K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
microprocessor chips;
reconfigurable architectures;
0.13 /spl mu/m CMOS technology;
0.13 micron;
166 MHz;
3 GHz;
DAPDNA-2;
clock frequency;
computation power;
computer architectures;
dynamically reconfigurable processor;
parallel data proce;
6.
A TLM platform for system-on-chip simulation and verification
机译:
用于片上模拟和验证的TLM平台
作者:
Xu S.
;
Pollitt-Smith H.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
C++ language;
circuit simulation;
formal verification;
hardware-software codesign;
integrated circuit design;
system-on-chip;
C++;
HDL simulation;
SOC design;
SystemC;
mixed language simulation environment;
reusable verification;
system-on-chip simulation;
system-on-;
7.
10-Gb/s SiGe modulator drivers with 4.5 V/sub pp/ output swing
机译:
10 GB / S SiGe调制器驱动器,具有4.5 V / SUB PP /输出摆幅
作者:
Day-Uei Li
;
Chia-Ming Tsai
;
Li-Ren Huang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
BiCMOS analogue integrated circuits;
Ge-Si alloys;
driver circuits;
integrated circuit design;
0.35 micron;
10 Gbit/s;
4.5 V;
BiCMOS technology;
SiGe;
SiGe modulator drivers;
cascode configuration;
cascode drivers;
double output swing;
silicon-based drivers;
8.
Challenges and opportunities in nano-scale VLSI design
机译:
纳米规模VLSI设计的挑战与机遇
作者:
Zhang K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
VLSI;
electronics industry;
integrated circuit design;
nanoelectronics;
VLSI chip;
active power management;
integrated circuit design;
microelectronics industry;
nano-scale VLSI design;
nanoelectronics;
9.
10 GB/s SiGe MODULATOR DRIVERS WITH 4.5 V{sub}(PP) OUTPUT SWING
机译:
10 GB / S SiGe调制器驱动器,具有4.5 V {Sub}(PP)输出摆幅
作者:
Day-Uei Li
;
Chia-Ming Tsai
;
Li-Ren Huang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
10.
Design and synthesis for timing error tolerance
机译:
定时误差容差的设计和合成
作者:
Shih-Chieh Chang
;
Cheng-Tao Hsieh
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
delays;
integrated circuit design;
integrated circuit yield;
statistical analysis;
timing;
delay variation;
design uncertainty;
fault correction;
process variation;
re-synthesis techniques;
sizing algorithms;
timing error tolerance;
triple module redundancy;
yield im;
11.
System-level design: a strategic investment for the future of the electronic industry
机译:
系统级设计:电子行业未来的战略投资
作者:
Sangiovanni-Vincentelli A.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
design for manufacture;
electronics industry;
integrated circuit design;
integrated circuit manufacture;
design for manufacture;
electronic system industry;
electronics industry;
integrated circuit design;
integrated circuit manufacture;
system-level design;
12.
Emerging memory technologies - mainstream or hearsay?
机译:
新兴的记忆技术 - 主流或传闻?
作者:
Natarajan S.
;
Alvandpour A.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
DRAM chips;
SRAM chips;
flash memories;
integrated circuit design;
integrated circuit technology;
system-on-chip;
DRAM;
Flash memories;
SRAM;
SoC market;
memory technology;
non-volatile memory;
silicon design process;
universal memory;
13.
An area and power efficient frame synchronizer for 480Mb/s OFDM-based UWB system
机译:
基于480MB / S OFDM的UWB系统的区域和功率高效帧同步器
作者:
Wei-Che Chang
;
Lin-Hung Chen
;
Wan-Chun Liao
;
Hsuan-Yu Liu
;
Chen-Yi Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
OFDM modulation;
circuit complexity;
matched filters;
receivers;
synchronisation;
ultra wideband communication;
0.18 micron;
480 Mbit/s;
CMOS process;
OFDM-based UWB system;
dynamic threshold design;
frame synchronizer;
improved matched filters;
14.
A 0.35/spl mu/m SiGe BiCMOS frequency synthesizer for WCDMA mobile terminals
机译:
WCDMA移动终端的0.35 / SPL MU / M SiGe BICMOS频率合成器
作者:
Jen-Lung Liu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
BiCMOS integrated circuits;
code division multiple access;
frequency division multiplexing;
frequency synthesizers;
radiofrequency oscillators;
voltage-controlled oscillators;
0.35 micron;
100 kHz;
14 mA;
200 musec;
2300 to 2360 MHz;
42 mA;
760 MHz;
FDD mode;
SiGe;
SiG;
15.
On statistical correlation based path selection for timing validation
机译:
基于统计相关性的定时验证路径选择
作者:
Kai Yang
;
Wang L.C.
;
Kwang-Ting Cheng
;
Sandip Kundu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit simulation;
fault tolerance;
network synthesis;
statistical analysis;
timing;
UR-Set;
circuit simulation;
error tolerance;
inter-die process variation;
intra-die process variation;
path selection methodology;
pattern-based analysis;
statistical correlation;
s;
16.
MIMCAP dynamic leakage impact to switched-capacitor sigma-delta converters in deep-submicron digital CMOS processes
机译:
Mimcap动态泄漏冲击对深亚微米数字CMOS流程中的开关电容Sigma-Delta转换器的影响
作者:
Weibiao Zhang
;
Yin Hu
;
Hisashi Shichijo
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS digital integrated circuits;
MIM devices;
capacitors;
leakage currents;
sigma-delta modulation;
switched capacitor networks;
130 nm;
MIMCAP;
digital CMOS processes;
dynamic leakage impact;
idle channel noise;
sigma-delta converters;
switched capacitor;
17.
ORC2DSP: Compiler Infrastructure Supports for VLIW DSP Processors
机译:
ORC2DSP:编译器基础架构支持VLIW DSP处理器
作者:
Cheng-Wei Chen
;
Chung-Lin Tang
;
Young-Chia Lin
;
Jenq-Kuen Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
18.
A mixed-signal implementation of a multi-carrier QAM transceiver for optical communications
机译:
用于光通信的多载波QAM收发器的混合信号实现
作者:
Azadet K.
;
Saibi F.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
digital integrated circuits;
mixed analogue-digital integrated circuits;
optical communication;
quadrature amplitude modulation;
signal processing;
subcarrier multiplexing;
transceivers;
SCM design specification constraints;
SCM modulation;
bandwidth efficient mo;
19.
How to make my chips cool power supply circuits
机译:
如何使我的芯片冷却电源电路
作者:
Peng-Chuang Huang
;
Chiu B.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
low-power electronics;
power consumption;
power supply circuits;
portable dvd player;
portable electronic;
portable handset;
power analysis;
power consumption;
power management technique;
power optimization;
slim dvd-rw;
20.
A new channel equalizer for OFDM-based wireless communications
机译:
基于OFDM的无线通信的新通道均衡器
作者:
Yuan-Mao Chang
;
Cheng-Wei Kuang
;
Chien-Ching Lin
;
Tzu-Shien Sang
;
Hsie-Chia Chang
;
Chen-Yi Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Doppler shift;
OFDM modulation;
Rayleigh channels;
adaptive equalisers;
adaptive estimation;
channel estimation;
frequency response;
interpolation;
maximum likelihood sequence estimation;
mobile communication;
1.5 dB;
2D linear interpolation;
30 Hz;
CFR;
Doppler frequ;
21.
A low-cost equalizer-based auto-gain-control scheme for high-speed transceiver applications
机译:
基于低成本的均衡器的自动增益控制方案,用于高速收发器应用
作者:
Lai J.J.
;
Chien-Hsiung Lee
;
Hsin-Shih Wang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic gain control;
equalisers;
intersymbol interference;
local area networks;
transceivers;
0.18 micron;
EQ-AGC;
Faraday cell library;
ISI;
UMC cell library;
equalizer-based auto-gain control;
fast Ethernet transceiver;
hardware complexity;
high-speed transceive;
22.
Test pattern generation and clock disabling for test time and power reduction
机译:
测试模式生成和时钟禁用测试时间和功率降低
作者:
Ji-Jan Chen
;
Kun-Lun Luo
;
Yeong-Jar Chang
;
Wen-Ching Wu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
clocks;
flip-flops;
integrated circuit testing;
clock disabling;
flip-flops;
pseudo-full scan architecture;
test pattern generation;
test vector sequence;
23.
A 0.35-/spl mu/m SiGe WCDMA direct conversion transmitter with DC offset compensation for carrier leakage reduction
机译:
一个0.35 / SPL MU / M SiGe WCDMA直接转换发射器,具有DC偏移补偿,用于减少载体泄漏
作者:
Peng-Un Su
;
Yen-Horng Chen
;
Tzu-Yi Yang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Ge-Si alloys;
code division multiple access;
gain control;
leakage currents;
radio transmitters;
radiofrequency integrated circuits;
0.35 micron;
2.7 V;
3.2 MHz;
46.4 mA;
DC offset compensation;
DC offset voltage;
SiGe;
WCDMA;
auto-calibration algorithm;
baseband filte;
24.
Decomposition of instruction decoder for low power designs
机译:
低功耗设计指令解码器的分解
作者:
Wu-An Kuo
;
TingTing Hwang
;
Wu A.C.H.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
decoding;
finite state machines;
hardware-software codesign;
instruction sets;
logic design;
low-power electronics;
microprocessor chips;
data path control signal;
frequently executed instruction groups;
instruction decoder decomposition;
instruction identificatio;
25.
A novel bubble tolerant thermometer-to-binary encoder for flash A/D converter
机译:
用于闪光A / D转换器的新型气泡容差的温度计对二元编码器
作者:
Yao-Jen Chuang
;
Hsin-Hung Ou
;
Bin-Da Liu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Gray codes;
analogue-digital conversion;
circuit simulation;
encoding;
integrated circuit design;
low-power electronics;
mixed analogue-digital integrated circuits;
thermometers;
Gray-ROM encoder;
bubble induced error reduction;
bubble tolerant thermometer-to-bina;
26.
A high-performance low power direct 2-D transform coding IP design for MPEG-4 AVC/H.264 with a switching power suppression technique
机译:
具有开关功率抑制技术的MPEG-4 AVC / H.264的高性能低功耗直接2-D转换编码IP设计
作者:
Kuan-Hung Chen
;
Jiun-In Guo
;
Kuo-Chuan Chao
;
Jinn-Shyan Wang
;
Yuan-Sun Chu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
digital signal processing chips;
integrated circuit design;
logic circuits;
low-power electronics;
transform coding;
very high speed integrated circuits;
video codecs;
video coding;
1.86 mW;
IP design;
MPEG-4 AVC/H.264;
data processing rate;
digital cinema video cod;
27.
An efficient power modeling approach for embedded memory using LIB format
机译:
利用lib格式实现嵌入式内存的有效功率建模方法
作者:
Wen-Tsan Hsieh
;
Chien-Nan Jimmy Liu
;
Yao-Feng Wang
;
Yi-Fang Chiu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
electronic design automation;
integrated circuit modelling;
memory architecture;
power consumption;
system-on-chip;
EDA tools;
LIB format;
SoC designs;
control signals;
dummy modular approach;
embedded memories;
embedded memory;
memory power estimation;
memory power;
28.
Low-power DIBITS Encoding with Register Relabeling for Instruction Bus
机译:
使用寄存器重新标记指令总线的低功耗Difits
作者:
Chin-Tzung Cheng
;
Wei-Hau Cbiao
;
Jean Jyh-Jiun Shann
;
Chung-Ping Chung
;
Wea-Feng Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Embedded system;
Low power;
Bus encoding;
BIBITS;
Register relabeling;
29.
High speed pilot-less sampling frequency acquisition for OFDM systems
机译:
OFDM系统的高速导频采样频率采集
作者:
Ching-Chi Chang
;
Chorng-Kuang Wang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
AWGN;
IEEE standards;
OFDM modulation;
frequency estimation;
iterative methods;
multipath channels;
signal sampling;
time-domain analysis;
AWGN;
CP;
IEEE 802.11a;
OFDM system;
cyclic prefix;
high speed sampling frequency acquisition;
multipath delay spread channels;
or;
30.
A novel current sensing circuit for a current-mode control CMOS DC-DC buck converter
机译:
电流模式控制CMOS DC-DC降压转换器的新型电流检测电路
作者:
Cheng-Hui Chang
;
Chang R.C.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
DC-DC power convertors;
circuit simulation;
current-mode circuits;
electric sensing devices;
integrated circuit design;
low-power electronics;
0.35 micron;
81.22 mW;
CMOS DC-DC buck converter;
TSMC;
current sensing circuit;
current-mode con;
31.
ToggleFinder: accurate RTL power estimation for large designs
机译:
ToggleFinder:大型设计的精确RTL功率估计
作者:
Ming-Yi Sum
;
Kai-Shuang Chang
;
Chia-Chien Weng
;
Shi-Yu Huang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
integrated circuit design;
logic design;
logic gates;
RTL power estimation;
ToggleFinder;
functional weighting scheme;
integrated circuit design;
large designs;
logic design;
logic gates;
multi-mode estimation methodology;
power characterization;
power mode classifi;
32.
Automatic generation of software/hardware co-emulation interface for transaction-level communication
机译:
用于事务级通信的软件/硬件共仿界面的自动生成
作者:
Young-Il Kim
;
Ki-Yong Aim
;
Heejun Shim
;
Wooseung Yang
;
Young-Su Kwon
;
Ando Ki
;
Chong-Min Kyung
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
circuit simulation;
design for testability;
hardware description languages;
hardware-software codesign;
integrated circuit design;
DUT protocol;
clock skew problem;
coemulation system;
emulator system protocol;
hardware emulator;
33.
Design techniques for INL and jitter prediction of a 3.3V 16b 65MSps pipeline ADC core
机译:
3.3V 16B 65MSP管道ADC芯的INL和抖动预测的设计技术
作者:
Zanchi A.
;
Tsay F.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
BiCMOS digital integrated circuits;
analogue-digital conversion;
circuit simulation;
0.4 micron;
1 MHz;
150 MHz;
16 bit;
3.3 V;
970 mW;
INL;
SiGe BiCMOS;
Spice;
circuit simulation;
jitter prediction;
pipeline ADC core;
34.
Low-power BIBITS encoding with register relabeling for instruction bus
机译:
使用寄存器重新标记用于指令总线的低功耗偏频
作者:
Chin-Tzung Cheng
;
Wei-Hau Chiao
;
Jean Jyh-Jiun Shann
;
Chung-Ping Chung
;
Wen-Feng Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Boolean functions;
embedded systems;
encoding;
low-power electronics;
peripheral interfaces;
system-on-chip;
Boolean functions;
address bus;
bit switchings;
bus encoding;
bus power;
bus-invert with transition signaling;
content-bus power reduction;
embedded system;
in;
35.
A background comparator calibration technique for flash analog-to-digital converters
机译:
闪光模数转换器的背景比较器校准技术
作者:
Chun-Cheng Huang
;
Jieh-Tsorng Wu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
calibration;
comparators (circuits);
high-speed integrated circuits;
integrated circuit design;
ADC transfer function;
background comparator calibration;
comparators;
device mismatches;
flash analog-to-digital;
36.
Dual-block-pipelined VLSI architecture of entropy coding for H.264/AVC baseline profile
机译:
用于H.264 / AVC基线配置文件的双块流水线VLSI架构熵编码
作者:
Tung-Chien Chen
;
Yu-Wen Huang
;
Chuan-Yong Tsai
;
Bing-Yu Hsieh
;
Liang-Gee Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
VLSI;
digital signal processing chips;
encoding;
hardware-software codesign;
instruction sets;
logic circuits;
variable length codes;
video coding;
100 MHz;
CAVLC;
H.264/AVC;
VLSI;
baseline profile;
context based adaptive variable length coding;
dual block pipelined a;
37.
On-chip bus encoding for LC cross-talk reduction
机译:
用于LC串扰减少的片上总线编码
作者:
Jiun-Sheng Huang
;
Shang-Wei Tu
;
Jing-Yang Jou
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit simulation;
delays;
encoding;
integrated circuit interconnections;
interference suppression;
system buses;
system-on-chip;
LC coupling delay;
LC cross talk reduction;
RC effects;
coupling delay reduction;
deep submicron technology;
global interconnect delay;
38.
A high linearity low noise amplifier in a 0.35/spl mu/m SiGe BiCMOS for WCDMA applications
机译:
用于WCDMA应用的0.35 / SPL MU / M SiGe Bicmos中的高线性低噪声放大器
作者:
Chih-Wei Wang
;
Yi-Bin Lee
;
Tzu-Yi Yang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
BiCMOS integrated circuits;
Ge-Si alloys;
UHF amplifiers;
code division multiple access;
0.35 micron;
1.65 dB;
2.7 V;
20 dB;
6.4 mA;
BiCMOS technology;
HBT;
P1dB;
QFN package;
SiGe;
WCDMA;
active biasing technique;
active feed circuit;
bias circuits;
low noise amplifier;
r;
39.
Efficient test scheduling for hierarchical core based design
机译:
基于分层核心设计的高效测试调度
作者:
Tai-Ping Wang
;
Cheng-Yu Tsai
;
Ming-Der Shieh
;
Kuen-Jone Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
automatic test software;
benchmark testing;
built-in self test;
integrated circuit testing;
system-on-chip;
SoC design hierarchy;
SoC test benchmarks;
SoC test scheduling;
core-based system-on-chip design;
dedicated TAM assignmen;
40.
Area and power efficient pattern prediction architecture for filter cache access prediction in the instruction memory hierarchy
机译:
用于指令存储层次结构中的过滤缓存访问预测的区域和功率有效模式预测架构
作者:
Bhattacharyya S.
;
Srikanthan T.
;
Vivekanandarajah K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
cache storage;
clocks;
computer power supplies;
memory architecture;
microprocessor chips;
semiconductor storage;
0.35 micron;
0.35/spl mu/ process technology;
MediaBench benchmark suite;
access prediction;
cache architecture;
embedded processor;
energy consumption;
41.
The limitations in applying analytic design equations for optimal class E RF power amplifiers design
机译:
应用分析设计方程对最优级RF功率放大器设计的限制
作者:
Lie D.Y.C.
;
Lee P.
;
Popp J.D.
;
Rowland J.F.
;
Ng H.H.
;
Yang A.H.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
UHF integrated circuits;
UHF power amplifiers;
circuit optimisation;
integrated circuit design;
microwave transistors;
network analysis;
system-on-chip;
transceivers;
300 to 2400 MHz;
RF transceiver products;
RF transmitter;
amplifier design;
analytic design equatio;
42.
A 0.35-μm SiGe WCDMA Direct Conversion Transmitter with DC Offset Compensation for Carrier Leakage Reduction
机译:
0.35微米的SiGe WCDMA直接转换发射器,具有DC偏移补偿,用于减少载体泄漏
作者:
Peng-Un Su
;
Yen-Horng Chen
;
Tzu-Yi Yang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
43.
A multiple-row transistor placement system for full custom design
机译:
用于全定制设计的多行晶体管放置系统
作者:
Yih-Chih Chou
;
Jian-Hung Chen
;
Yang M.
;
Shyh-Chang Lin
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit layout CAD;
insulated gate field effect transistors;
integrated circuit layout;
network routing;
automatic generated transistor layout;
automatic transistor placer;
gate swapping;
gate transistors;
layout design;
manual optimization;
multiple-row transisto;
44.
System-level HW/SW co-simulation framework for multiprocessor and multithread SoC
机译:
用于多处理器和多线程SoC的系统级HW / SW共模谱框架
作者:
Moo-Kyoung Chung
;
Sangjun Yang
;
Sang-Hoon Lee
;
Chong-Min Kyung
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
C++ language;
circuit simulation;
hardware-software codesign;
microprocessor chips;
system-on-chip;
C language;
C++ language;
POSIX API;
RTOS scheduler;
SoC design;
SpecC;
SystemC;
clock events;
cosimulation framework;
hardware description;
high-level co-simulation;
leg;
45.
Fast switching gigabit/s CMOS burst-mode transmitter for PON applications
机译:
用于PON应用程序的快速切换千兆/ S CMOS突发模式发送器
作者:
Day-Uei Li
;
Chia-Ming Tsai
;
Li-Ren Huang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
driver circuits;
low-power electronics;
network synthesis;
optical transmitters;
passive networks;
power integrated circuits;
semiconductor lasers;
switching circuits;
0.25 micron;
1310 nm;
2.5 Gbit/s;
84 ps;
97 ps;
EPON;
Fabry-Perol laser dio;
46.
New architectures for reduced-state sequence detection with local feedback
机译:
具有局部反馈的降低状态序列检测的新架构
作者:
Haratsch E.F.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Viterbi detection;
channel estimation;
maximum likelihood sequence estimation;
state feedback;
Viterbi detectors;
add-compare operation;
channel memory;
local feedback;
reduced-state sequence detection;
select operation;
47.
Lightweight arithmetic units for VLSI digital signal processors
机译:
VLSI数字信号处理器的轻量级算术单元
作者:
Shih-Hao Ou
;
Tay-Jyi Lin
;
Hung-Yueh Lin
;
Chie-Min Chao
;
Chie-WeiLiu
;
Chein-Wei Jen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
IEEE standards;
VLSI;
circuit optimisation;
digital signal processing chips;
floating point arithmetic;
logic design;
16 bit;
32 bit;
40.18 dB;
IEEE single-precision floating-point arithmetic;
VLSI digital signal processors;
embedded signal processing;
hardware comp;
48.
Delay modeling for buffered RLY/RLC trees
机译:
缓冲RLY / RLC树延迟建模
作者:
Sheng-Lung Wang
;
Yao-Wen Chang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
SPICE;
circuit simulation;
delays;
integrated circuit interconnections;
integrated circuit modelling;
synchronisation;
HSPICE;
buffer insertion;
buffered RLY/RLC trees;
circuit delay modeling;
deep submicron circuits;
high performance circuits;
49.
Delay defect coverage for FPGA test configurations based on statistical evaluation
机译:
基于统计评估的FPGA测试配置延迟缺陷覆盖
作者:
Hsiang-Chieh Liao
;
Jing-Jia Liou
;
Yen-Lin Peng
;
Chih-Tsun Huang
;
Cheng-Wen Wu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
fault simulation;
field programmable gate arrays;
integrated circuit testing;
reconfigurable architectures;
statistical analysis;
FPGA performance testing;
FPGA test configurations;
delay defect coverage;
evaluation algorithm;
pe;
50.
A dual-band transmitter for IEEE 802.11a/b/g WLAN
机译:
用于IEEE 802.11a / b / g wlan的双频发射器
作者:
Yi-Bin Lee
;
Chun-Lin Ko
;
Ming-Ching Kuo
;
Peng-Un Su
;
Tzu-Yi Yang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
IEEE standards;
OFDM modulation;
frequency synthesizers;
quadrature amplitude modulation;
transmitters;
voltage-controlled oscillators;
wireless LAN;
0.25 micron;
2.4 GHz;
2.5 V;
36 dB;
5 GHz;
63 mA;
64-QAM OFDM mode;
82 mA;
CMOS process;
EVM;
IE;
51.
Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution
机译:
用于多个固定宽度指令集和条件执行的指令集架构方案
作者:
Bor-Sung Liang
;
June-Yuh Wu
;
Jih-Yiing Lin
;
Ming-Chuan Huang
;
Chi-Shaw Lai
;
Yun-Yin Lien
;
Ching-Hua Chang
;
Pei-Lin Tsai
;
Ching-Peng Lin
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
embedded systems;
instruction sets;
microprocessor chips;
reduced instruction set computing;
ISA scheme;
PCE;
code size;
conditional execution method;
embedded RISC processor;
execution cycle;
instruction set architecture scheme;
multiple fixed-width instruction se;
52.
Design and implementation of an efficient architecture for higher order statistics with DWT
机译:
DWT的高阶统计数据的设计与实现
作者:
Lih-yih Chiou
;
Hsieh-wei Lee
;
Sheau-Fang Lei
;
Bin-Da Liu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
VLSI;
circuit layout;
digital signal processing chips;
discrete wavelet transforms;
hardware description languages;
hardware-software codesign;
higher order statistics;
logic circuits;
low-power electronics;
spectral analysis;
DWT bit streams;
biomedical applicatio;
53.
Adaptive on-die termination resistors for high-speed transceiver
机译:
用于高速收发器的自适应上终端电阻
作者:
Chih Hsien Lin
;
Chih-Ning Chen
;
Shyh-Jye Jou
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
coaxial cables;
impedance matching;
resistors;
transceivers;
0.18 micron;
CMOS process;
characteristic impedance;
coaxial cable;
data transmission;
high-speed transceiver;
impedance matching;
on-die termination resistors;
serial link transce;
54.
A novel register organization for VLIW digital signal processors
机译:
用于VLIW数字信号处理器的新型寄存器组织
作者:
Tay-Jyi Lin
;
Chen-Chia Lee
;
Chih-Wei Liu
;
Chein-Wei Jen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
digital signal processing chips;
instruction sets;
shift registers;
VLIW DSP;
VLIW digital signal processors;
register file;
register organization;
55.
PARSY: a parasitic symmetric router for net bundles using module generators
机译:
Parsy:使用模块生成器的网捆绑的寄生对称路由器
作者:
Schreiner L.
;
Olbrich M.
;
Barke E.
;
Meyer zu Bexten V.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
analogue integrated circuits;
integrated circuit interconnections;
integrated circuit layout;
network routing;
PARSY;
analog signal interconnect;
equalized wirelength;
module generators;
net bundles;
paired nets;
parasitic symmetric router;
56.
A multilevel sensing and program verifying scheme for Bi-NAND flash memories
机译:
Bi-NAND闪存的多级传感和程序验证方案
作者:
Chiu-Chiao Chung
;
Hongchin Lin
;
You-Min Shen
;
Yen-Tai Lin
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
NAND circuits;
cellular arrays;
circuit simulation;
flash memories;
semiconductor device models;
sensor fusion;
Bi-NAND flash memory;
advanced cross coupled sense amplifier;
cell arrays;
mismatch effect immunity;
multilevel sensing circuit;
program verifying scheme;
57.
0RC2DSP: compiler infrastructure supports for VLIW DSP processors
机译:
0RC2DSP:编译器基础架构支持VLIW DSP处理器
作者:
Cheng-Wei Chen
;
Chung-Lin Tang
;
Young-Chia Lin
;
Jenq-Kuen Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
digital signal processing chips;
electronic design automation;
hardware-software codesign;
instruction sets;
integrated circuit design;
program compilers;
0RC2DSP;
32 bit;
ORC infrastructures;
PAC architectures;
PAC core;
VLIW DSP processors;
compiler infrastructure;
58.
A 528MS/s frequency synchronizer for OFDM-based UWB system
机译:
基于OFDM的UWB系统的528ms / s频率同步器
作者:
Lin-Hung Chen
;
Wei-Che Chang
;
Hsuan-Yu Liu
;
Chen-Yi Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
OFDM modulation;
low-power electronics;
synchronisation;
ultra wideband technology;
0.18 micron;
528 mHz;
CMOS process;
OFDM;
UWB system;
data partition;
frequency synchronizer;
low-power scheme;
power consumption;
59.
An improved methodology for system-level point-to-point communication architecture synthesis in SOC design
机译:
SoC设计中系统级点对点通信架构合成的改进方法
作者:
Hao-Yueh Hsieh
;
Bo-Wei Chen
;
Ting-Chi Wang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
integrated circuit design;
network analysis;
system-on-chip;
SOC design;
communication energy;
point-to-point communication architecture synthesis;
wirelength;
60.
A 0.35μm SiGe BiCMOS Frequency Synthesizer for WCDMA Mobile Terminals
机译:
用于WCDMA移动终端的0.35μmSiGeBICMOS频率合成器
作者:
Jen-Lung Liu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
61.
Timing recovery methods for gigabit Ethernet
机译:
千兆以太网时序恢复方法
作者:
Yin Hu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
clocks;
integrating circuits;
interpolation;
local area networks;
network topology;
phase locked loops;
synchronisation;
timing circuits;
twisted pair cables;
analog interpolating method;
category-5 cable;
clock control;
clock dividing;
digit;
62.
Low-power test pattern generator design for BIST via non-uniform cellular automata
机译:
通过非均匀蜂窝自动机的BIST进行低功耗测试模式发生器设计
作者:
Kilic H.
;
Oktem L.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
built-in self test;
cellular automata;
computational complexity;
electronic engineering computing;
integrated circuit testing;
BIST;
NP-complete;
built-in self-test;
fault-coverage;
low-power design topology;
low-power test patter;
63.
A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer
机译:
1.6-GHz Delta-Sigma调制分数-N频率合成器
作者:
Ching-Yuan Yang
;
Kuei-Zu Jiang
;
Jen-Wen Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
UHF oscillators;
delta-sigma modulation;
frequency synthesizers;
low-power electronics;
phase locked loops;
voltage-controlled oscillators;
0.18 micron;
1.6 GHz;
1.8 V;
29.05 mW;
CMOS technology;
IEEE 802.11 b/g channels;
LC-tank oscillator;
64.
An accurate design of fully integrated 2.4GHz CMOS cascode LNA
机译:
完全集成的2.4GHz CMOS Cascode LNA精确设计
作者:
Chih-Ho Tu
;
Ying-Zong Juang
;
Chin-Fong Chiu
;
Ruey-Lue Wang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS analogue integrated circuits;
UHF amplifiers;
UHF integrated circuits;
circuit layout;
integrated circuit design;
network topology;
0.25 micron;
11 mW;
13.29 dB;
1dB gain compression point;
2 V;
2.4 GHz;
2.87 dB;
5.5 mA;
CMOS;
P1dB;
cascode LNA;
electromagnetic anal;
65.
Reconfigurable cryptographic RISC microprocessor
机译:
可重新配置的加密RISC微处理器
作者:
Smyth N.
;
McLoone M.
;
McCanny J.V.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
cryptography;
microprocessor chips;
reconfigurable architectures;
reduced instruction set computing;
cryptographic microprocessor;
embedded security-processing system;
hash algorithm;
private-key algorithm;
reconfigurable cryptographic RISC microprocessor;
reduce;
66.
An efficient and low power systolic squarer
机译:
高效且低功耗的收缩方块
作者:
Yuan-Long Jeang
;
Liang-Bi Chen
;
Jiun-Hau Tu
;
Ing-Jer Huang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
adders;
digital signal processing chips;
flip-flops;
low-power electronics;
systolic arrays;
0.35 micron;
D flip flops;
digital signal processing chips;
full adder;
low power electronics;
low power systolic squarer;
systolic array;
67.
High accuracy jitter measurement using cyclic pulse width modulation structure
机译:
使用循环脉冲宽度调制结构的高精度抖动测量
作者:
Kuo-Hsing Cheng
;
Shu-Yu Jiang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
built-in self test;
integrated circuit testing;
jitter;
logic testing;
pulse width modulation;
0.25 micron;
BIST;
PVTL;
built in self test;
clock jitter measurement;
cyclic pulse width modulation structure;
high accuracy jitter measurement;
high-speed circuit testin;
68.
Faster min-cut computation in unweighted hypergraphs/circuit netlists
机译:
在未加权的超图/电路网手中更快地切割计算
作者:
Wai-Kei Mak
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit analysis computing;
circuit optimisation;
graph theory;
circuit partitioning;
hypergraph minimum cut algorithm;
min-cut computation;
minimum s-t cut;
unweighted hypergraphs/circuit netlists;
69.
On improving dynamic range of wideband multistage /spl Sigma//spl Delta/ modulator using nonlinear oscillation
机译:
用非线性振荡改进宽带多级/ SPL SIGMA // SPL DELTA /调制器的动态范围
作者:
Teng-Hung Chang
;
Lan-Rong Dung
;
Jwin-Yen Guo
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit simulation;
interference suppression;
modulators;
resonators;
sigma-delta modulation;
signal sampling;
HQCRFF;
LQCIFF;
MASH;
dynamic range improvement;
high-Q cascade-of-resonator-with-feedforward;
in-band quantization noise;
low-Q cascade-of-integrator-with;
70.
Platform based design of all binary motion estimation (ABME) with bus interleaved architecture
机译:
基于平台的所有二进制运动估计(ABME)的设计与总线交错架构
作者:
Shih-Hao Wang
;
Wei-Lun Tao
;
Chung-Neng Wang
;
Wen-Hsiao Peng
;
Tihao Chiang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
adders;
digital signal processing chips;
hardware description languages;
hardware-software codesign;
system buses;
2D mapping unit;
all binary motion estimation;
binarized data;
binary adder tree;
block matching metric;
bus bandwidth reduction scheme;
bus interleav;
71.
System-level performance analysis of embedded system using behavioral C/C++ model
机译:
使用行为C / C ++模型的嵌入式系统的系统级性能分析
作者:
Moo-Kyoung Chung
;
Sangkwon Na
;
Chong-Min Kyung
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
C++ language;
circuit simulation;
embedded systems;
hardware-software codesign;
instruction sets;
integrated circuit modelling;
system-on-chip;
C language;
C++ language;
HIPA;
IP models;
SoC design flow;
behavioral model;
communication architecture;
cosimulation tools;
72.
Substrate-bias optimized 0.18/spl mu/m 2.5GHz 32-bit adder with post-manufacture tunable clock
机译:
基板偏置优化0.18 / SPL MU / M 2.5GHz 32位加法器,具有制造后可调时钟
作者:
Qi-Wei Kuo
;
Vikas Sharma
;
Charlie Chung-Ping Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
adders;
circuit optimisation;
clocks;
power supply circuits;
0.18 micron;
2.5 GHz;
32 bit;
32bit Han-Carlson adder;
CMOS technology;
TSMC;
linear clock tunability;
low power-delay product;
post-manufacture tunable clock;
power delay improveme;
73.
Embedded memory diagnostic data compression using differential address
机译:
使用差分地址嵌入式内存诊断数据压缩
作者:
Chin-Lung Su
;
Rei-Fu Huang
;
Cheng-Wen Wu
;
Yeong-Jar Chang
;
Shen-Tien Lin
;
Wen-Ching Wu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
built-in self test;
design for testability;
integrated circuit testing;
integrated memory circuits;
logic testing;
built-in self-diagnosis;
differential address level;
embedded memory diagnostic data compression;
integrated circuit testing;
logic testing;
memory B;
74.
A semi-custom design of branch address calculator in the IBM power4 microprocessor
机译:
IBM Power4微处理器中分支地址计算器的半定制设计
作者:
Pong-Fei Lu
;
Northrop G.A.
;
Chiarot K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
IBM computers;
calculating apparatus;
circuit optimisation;
logic design;
microprocessor chips;
silicon-on-insulator;
0.18 micron;
1.7 GHz;
IBM power4 microprocessor;
IFU;
SOI technology;
circuit optimization;
flexible custom circuit design;
instruction fetch unit;
po;
75.
A hardware/software-concurrent JPEG2000 encoder
机译:
硬件/软件 - 并发JPEG2000编码器
作者:
Wen-Chi Yen
;
An-Chi Chen
;
Po-Sheng Liu
;
Youn-Long Lin
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
data compression;
discrete wavelet transforms;
hardware-software codesign;
image coding;
system-on-chip;
DWT coding;
EBCOT Tier-1 coding;
JPEG2000 encoder;
SOC platform;
hardware accelerator IP;
hardware software codesign;
76.
Hardware implementations of high-speed network monitors
机译:
高速网络监视器的硬件实现
作者:
Tanba H.
;
Yamada Y.
;
Kitamichi J.
;
Kurda K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
Internet;
application specific integrated circuits;
computer networks;
field programmable gate arrays;
high-speed techniques;
integrated circuit design;
logic design;
monitoring;
telecommunication security;
telecommunication traffic;
ASIC;
FPGA;
IP flooding detectio;
77.
A low-power H.264/AVC decoder
机译:
低功耗H.264 / AVC解码器
作者:
Ting-An Lin
;
Tsu-Ming Liu
;
Chen-Yi Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
decoding;
digital signal processing chips;
hardware description languages;
hardware-software codesign;
integrated circuit design;
logic circuits;
low-power electronics;
video codecs;
1080HD video sequence;
88 mW;
H.264/AVC decoder;
gated clock technique;
hierarchica;
78.
On-chip network evolution using NetC
机译:
使用netc的片上网络演进
作者:
Liwei Ma
;
Yihe Sun
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
hardware description languages;
hardware-software codesign;
integrated circuit design;
integrated circuit interconnections;
network topology;
system-on-chip;
NetC;
SoC;
SystemC programs;
description language;
interconnection;
network design;
network interconnections;
79.
A 1.25Gb/s half-rate clock and data recovery circuit
机译:
1.25GB / s半速率时钟和数据恢复电路
作者:
Ching-Yuan Yan
;
Cheng-Hsing Lee
;
Yu Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
phase detectors;
synchronisation;
voltage-controlled oscillators;
0.35 micron;
1.25 Gbit/s;
3 V;
54.8 mW;
625 Mbit/s;
CDR circuit;
NRZ data stream;
VCO;
clock and data recovery circuit;
half-rate phase detector;
locked condition;
power consump;
80.
JPEG2000 encoder architecture design with fast EBCOT algorithm
机译:
JPEG2000编码器架构设计与快速EBCOT算法
作者:
Tsung-Han Tsai
;
Lian-Tsung Tsai
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
computational complexity;
digital signal processing chips;
image coding;
integrated circuit design;
logic circuits;
low-power electronics;
parallel architectures;
0.25 micron;
40 MHz;
EBCOT algorithm;
JPEG2000 encoder;
SNR scalability;
architecture design;
context mo;
81.
A 10-Gb/s laser diode driver in 0.35 /spl mu/m BiCMOS technology
机译:
0.35 / SPL MU / M BICMOS技术的10 GB / S激光二极管驱动器
作者:
Teng-Yi Wang
;
Wei-Zen Chen
;
Chia-Ming Tsai
;
Li-Ren Huang
;
Day-Uei Li
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
BiCMOS integrated circuits;
SONET;
digital signal processing chips;
driver circuits;
high-speed integrated circuits;
local area networks;
network synthesis;
optical modulation;
0.35 micron;
1.38 W;
10 Gbit/s;
10G Ethernet;
3.3 V;
40 to 100 mA;
47 ps;
7 V;
BiCMOS technol;
82.
Race-condition-aware retiming
机译:
种族条件感知重新定位
作者:
Shih-Hsu Huang
;
Feng-Pin Lu
;
Wei-Chieh Yu
;
Yow-Tyng Nieh
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
circuit analysis computing;
clocks;
timing circuits;
clock cycle time;
clock period reduction;
critical hold constraints;
delay insertion;
race-condition-aware retiming;
retiming transformation;
83.
Buffered tree refinement considering timing and congestion
机译:
考虑定时和拥塞缓冲树质细化
作者:
Wei-Zhi Ye
;
Ting-Chi Wang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
buffer circuits;
network routing;
table lookup;
tree searching;
buffered tree refinement;
congestion cost;
look-up tables;
timing improvements;
84.
The design of a DSC/DV dual role backend SoC
机译:
DSC / DV双角色后端SoC的设计
作者:
Lee C.L.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
data compression;
discrete cosine transforms;
integrated circuit design;
microcontrollers;
quantisation (signal);
system-on-chip;
video codecs;
video coding;
32 bits;
96 MHz;
DCT;
DV;
JPEG/MPEG-4 SP codec engine;
MPEG-4 compression;
RISC engine;
SC;
VGA video;
codec modu;
85.
SPEED: synthesis of high-performance large scale analog/mixed signal circuit
机译:
速度:高性能大规模模拟/混合信号电路的合成
作者:
Yu-Tsun Chien
;
Li-Ren Huang
;
Wen-Tzao Chen
;
Gin-Kou Ma
;
Mukherjee T.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
analogue-digital conversion;
circuit simulation;
integrated circuit design;
integrated circuit noise;
mixed analogue-digital integrated circuits;
13 bit;
3.3 V;
364 mW;
73.8 dB;
SPEED;
analog to digital converter;
cell level analog synthesis;
chip fabrication;
large;
86.
CyberWorkBench: integrated design environment based on C-based behavior synthesis and verification
机译:
CyberWorkbench:基于C基行为合成和验证的集成设计环境
作者:
Wakabayashi K.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
C language;
circuit CAD;
formal verification;
hardware-software codesign;
integrated circuit layout;
large scale integration;
C language;
C synthesis;
CyberWorkBench;
RTL design;
configurable processor;
hardware design;
high level synthesis;
industrial design;
integra;
87.
Analog baseband filtering realized using switched capacitor finite impulse response filter
机译:
使用开关电容有限脉冲响应滤波器实现模拟基带滤波
作者:
Dabrowski A.
;
Dlugosz R.
;
Pawtowski P.
;
Iniewski K.
;
Gaudet V.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
FIR filters;
cellular radio;
code division multiple access;
discrete time filters;
switched capacitor filters;
CMOS;
FIR;
GSM channel filter;
GSM/WCDMA application;
SC technique;
analog baseband filtering;
baseband channel filters;
discrete;
88.
Future trends in SoC interconnect
机译:
SoC互连的未来趋势
作者:
Furber S.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
asynchronous circuits;
electronic design automation;
integrated circuit design;
integrated circuit interconnections;
network topology;
system-on-chip;
IP block;
SoC interconnect;
correct-by-construction;
design automation software;
network design;
self timed packet;
89.
A DVB-T baseband demodulator design based on multimode silicon IPs
机译:
基于多模硅IPS的DVB-T基带解调器设计
作者:
Kai-Yuan Jheng
;
Tsung-Han Wu
;
Yi-Chiuan Wang
;
Jih-Chiang Yeo
;
Yu-Ju Cho
;
An-Yeu Wu
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
VLSI;
broadcasting;
circuit simulation;
demodulators;
industrial property;
DVB-T baseband demodulator;
FEC;
FFT;
Simulink;
channel equalizer;
channel estimator;
deinterleavers;
descrambler;
multimode silicon IP;
system-level simulation;
90.
Transient analysis of thermal noise on switch cap circuit
机译:
开关帽电路热噪声的瞬态分析
作者:
Pao Cheng Chiu
;
Chao Cheng Lee
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
analogue-digital conversion;
circuit simulation;
integrated circuit modelling;
mixed analogue-digital integrated circuits;
switched capacitor filters;
thermal noise;
transient analysis;
10 bit;
4KTR thermal noise;
AC equivalent model;
circuit simulation;
mathematic;
91.
All digital 625Mbps 2.5Gbps deskew buffer design
机译:
所有数字625Mbps&2.5Gbps歪斜缓冲设计
作者:
Hung-Wen Lu
;
Yin-Tin Chang
;
Chau-Chin Su
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
buffer circuits;
high-speed integrated circuits;
integrated circuit design;
phase detectors;
0.18 micron;
16 mW;
2.5 Gbit/s;
3.8 mW;
625 Mbit/s;
TSMC;
all digital deskew buffer design;
circuit complexity reduction;
confidence counter;
data re;
92.
Parallel core testing with multiple scan chains by test vector overlapping
机译:
通过测试向量重叠使用多个扫描链的平行核心测试
作者:
Shinogi T.
;
Yamada Y.
;
Hayashi T.
;
Yoshikawa T.
;
Tsuruoka S.
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
automatic testing;
built-in self test;
integrated circuit testing;
parallel architectures;
system-on-chip;
I/O pins;
SoC test vector overlapping;
controller design;
multiple scan chains;
parallel core testing;
scan architecture;
93.
Substrate-Bias Optimized 0.18μm 2.5GHz 32-bit Adder with Post-Manufacture Tunable Clock
机译:
基板偏置优化0.18μm2.5GHz 32位加法器,制造后可调时钟
作者:
Qi-Wei Kuo
;
Vikas Sharma
;
Charlie Chung-Ping Chen
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
94.
Architecture design of MPEG-4 texture decoder supporting object-based video coding
机译:
基于对象的视频编码的MPEG-4纹理解码器建筑学设计
作者:
Hui-Cheng Hsu
;
Chang N.Y.-C.
;
Tian-Sheuan Chang
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
digital signal processing chips;
image texture;
logic circuits;
low-power electronics;
system-on-chip;
variable length codes;
video codecs;
0.18 micron;
0.92 mW;
CIF@30FPS;
MPEG-4 texture decoder;
decoder architecture design;
embedded video codec systems;
object-base;
95.
Formal compliance verification of interface protocols
机译:
界面协议的正式合规性验证
作者:
Ya-Ching Yang
;
Juinn-Dar Huang
;
Chia-Chih Yen
;
Che-Hua Shih
;
Jing-Yang Jou
会议名称:
《IEEE VLSI-TSA International Symposium on VLSI Design》
|
2005年
关键词:
computational complexity;
finite state machines;
formal verification;
logic design;
protocols;
system-on-chip;
tree searching;
SoC;
branch-and-bound algorithm;
finite state machines;
formal compliance verification;
interface logic;
interface protocol compliance veri;
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