On-chip bus encoding for LC cross-talk reduction

摘要

With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, as the working frequency of integrated circuits increasing above GHz, the inductive crosstalk will also have very significant influence on the global interconnect delay. However, most existing works consider only RC effects (the worst-case switching pattern resulting from coupling capacitance), to develop their encoding schemes to reduce bus delay. In this paper, the authors proposed a flexible bus encoding method to reduce the LC coupling delay on on-chip bus with a user-given bus structure, the working frequency, and the delay constraint. Simulation results show that our encoding method can significantly reduce the coupling delay of a bus according to the delay constraint.