Substrate-bias optimized 0.18/spl mu/m 2.5GHz 32-bit adder with post-manufacture tunable clock

摘要

In this paper, we present a 32bit Han-Carlson adder that operates at 2.56GHz and is based on TSMC 0.18/spl mu/m bulk CMOS technology. In this work, we optimize the substrate bias of the adder core to achieve a low power-delay product for low power and high speed purposes, and use a post-manufacture tunable clock structure that manipulates the clock at post-fabrication stage to compensate for the process dependent violation to the timing. Simulation results have shown that the substrate-bias optimization results in a 37% of power delay improvement and utilization of tunable delay elements achieve 50 ps of almost linear clock tunability.