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IEEE Asian Solid State Circuits Conference
IEEE Asian Solid State Circuits Conference
召开年:
2014
召开地:
Kaohsiung(TW)
出版时间:
-
会议文集:
-
会议论文
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1.
A 4.9 mW neural network task scheduler for congestion-minimized network-on-chip in multi-core systems
机译:
用于多核系统中拥塞最小的片上网络的4.9 mW神经网络任务调度程序
作者:
Youchang Kim
;
Gyeonghoon Kim
;
Injoon Hong
;
Donghyun Kim
;
Hoi-Jun Yoo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
augmented reality;
multiprocessing systems;
network-on-chip;
neural nets;
power aware computing;
processor scheduling;
NNTS;
NOTA;
NoC communication pattern;
NoC-based multicore SoC;
RP-NNA;
augmented reality applications;
congestion-minimized network-on-chip;
energy efficiency;
multicore systems;
near-optimal task assignment algorithm;
network congestion;
neural network task scheduler;
power 4.9 mW;
reconfigurable precision neural network accelerator;
Accuracy;
Artificial neural networks;
Neurons;
Piecewise linear approximation;
System-on-chip;
Throughput;
network congestion;
network-on-chip (NoC);
neural network (NN);
task assignment;
2.
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator
机译:
具有4.5至13倍节能的嵌入式微处理器,带有主要静态/部分动态可重构阵列加速器
作者:
Hida Itaru
;
Kim Dongkyu
;
Asai Tetsuya
;
Motomura Masato
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
microprocessor chips;
reconfigurable architectures;
DYNaSTA accelerator;
energy-efficient embedded microprocessor;
fabricated chip measurements;
heavily-recursively executed small code segments;
hybrid architecture;
mainly-static-partially-dynamic reconfigurable array accelerator;
Arrays;
Clocks;
Frequency measurement;
Power demand;
Power measurement;
Registers;
Semiconductor device measurement;
3.
A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation
机译:
人体偏置发生器,具有宽泛的电源范围,低至阈值电压,可进行芯片内可变性补偿
作者:
Kamae Norihiro
;
Mahfuzul Islam A.K.M.
;
Tsuchiya Akira
;
Onodera Hidetoshi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
amplifiers;
charge pump circuits;
low-power electronics;
system-on-chip;
BBG;
FGBB;
Vth biasing scheme;
body bias generator;
cell-based design;
core supply voltage;
fine-grain body biasing;
forward body bias voltages;
internal switched-capacitor charge pumping;
low power CMOS process;
low voltage error amplifier;
reverse body bias voltages;
size 65 nm;
voltage 500 mV to 1.2 V;
within-die variability compensation;
Capacitors;
Charge pumps;
Conferences;
Generators;
Substrates;
Threshold voltage;
Voltage measurement;
4.
A low-power single-chip transceiver for 169/300/400/900 MHz band wireless sensor networks
机译:
用于169/300/400/900 MHz频段无线传感器网络的低功耗单芯片收发器
作者:
Oba Makoto
;
Okada Etienne
;
Tachibana Ayako
;
Takahashi Koichi
;
Sagisaka Masahiko
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
frequency shift keying;
low-power electronics;
radio transceivers;
wireless sensor networks;
CMOS;
GFSK modulation;
MAC layer;
RF frontend;
bit rate 1.2 kbit/s to 200 kbit/s;
current 23 mA;
digital baseband;
frequency 169 MHz;
frequency 300 MHz;
frequency 400 MHz;
frequency 900 MHz;
frequency 915 MHz;
low-power transceiver;
sub-GHz frequency bands;
voltage 3.3 V;
wireless sensor networks;
Active inductors;
CMOS integrated circuits;
Frequency shift keying;
Harmonic analysis;
Transceivers;
Wireless sensor networks;
Active Inductor;
Harmonic-Rejection;
Low-Power;
Single-Chip;
Wireless Sensor Networks;
5.
A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface
机译:
用于具有直接数字接口的包络跟踪应用的20MS / s降压/升压电源调制器
作者:
Shang-Hsien Yang
;
Chin-Long Wey
;
Ke-Horng Chen
;
Ying-Hsi Lin
;
Jing-Jia Chen
;
Tsung-Yen Tsai
;
Chao-Cheng Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
digital-analogue conversion;
modulators;
power convertors;
radiofrequency power amplifiers;
system-on-chip;
4G LTE RF power amplifier envelope tracking applications;
4G LTE RF-PA envelope tracking applications;
BBSM;
H-bridges;
buck-boost supply modulator;
current sources;
current-steering DAC-like supply modulator;
digital LTE baseband SoC;
direct digital interface;
efficiency 75 percent;
open-loop topology;
power 2.8 W;
word length 4 bit;
Bandwidth;
Inductors;
Linearity;
Long Term Evolution;
Modulation;
Power amplifiers;
Radio frequency;
Supply modulator;
envelope tracking;
non-inverting buck/boost converter;
6.
A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuit
机译:
具有瞬态优化反馈电路的单片电容电流控制磁滞降压转换器
作者:
Shih-Hsiung Chien
;
Ting-Hsuan Hung
;
Szu-Yu Huang
;
Tai-Haur Kuo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
circuit feedback;
power convertors;
CMOS;
current 500 mA;
dynamic voltage scaling;
monolithic capacitor-current-controlled hysteretic buck converter;
power 500 mW;
size 0.35 mum;
time 0.9 mus;
time 3 mus;
transient-hold technique;
transient-optimized feedback circuit;
voltage 0.6 V;
Capacitors;
Current measurement;
Feedback circuits;
System-on-chip;
Transient analysis;
Transient response;
Voltage control;
DC-DC buck converter;
DVS;
capacitor-current sensor;
dynamic voltage scaling;
fast transient response;
7.
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability
机译:
具有10年数据保留能力的基于2.4 pJ铁电的非易失性触发器
作者:
Kimura Hiromitsu
;
Fuchikami Takaaki
;
Maramoto Kyoji
;
Fujimori Yoshikazu
;
Izumi Shintaro
;
Kawaguchi Hitoshi
;
Yoshimoto Masahiko
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
ferroelectric devices;
flip-flops;
large scale integration;
logic circuits;
low-power electronics;
random-access storage;
CMOS;
FE capacitors;
NWF;
PZT;
capacitor size reduction;
energy 2.4 pJ;
ferroelectric-based nonvolatile flip-flop;
leakage current;
logic circuit;
low-power LSL;
nonvolatile storage capability;
power consumption;
power gating implementation;
short-term data retention;
size 130 nm;
temperature 85 degC;
thin films;
time 1.6 mus;
time 10 hour;
time 10 year;
time 170 ns;
vital sensor;
voltage 1.5 V;
voltage 240 mV;
word length 32 bit;
CMOS integrated circuits;
Capacitors;
Flip-flops;
Iron;
Large scale integration;
Logic circuits;
Power supplies;
Ferroelectric capacitor;
Low power;
Microporcessor;
Non-volatile flip-flop;
Non-volatile logic;
8.
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer
机译:
CMOS宽带LNA混频器的前馈噪声和失真消除技术
作者:
Chi-Fu Li
;
Shih-Chieh Chou
;
Chang-Ming Lai
;
Cuei-Ling Hsieh
;
Liu Jenny Yi-Chun
;
Po-Chiun Huang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
UHF mixers;
low noise amplifiers;
CMOS broadband LNA-mixer;
CMOS process;
IM3;
LNA noise;
auxiliary feedforward path;
bandwidth 2 GHz;
circuit technique;
cross-coupled active mixers;
current 7.7 mA;
distortion cancellation technique;
feedforward noise;
frequency 900 MHz;
gain 19 dB;
linearity performance;
mixer output;
noise figure;
noise figure 2.7 dB;
noise figure 6.2 dB;
power consumption;
power overhead;
shunt-feedback LNA;
signal bandwidth;
size 0.18 mum;
test circuit;
third-order intermodulation distortion;
voltage 1.8 V;
voltage gain;
Feedforward neural networks;
Linearity;
Mixers;
Noise cancellation;
Transconductance;
Wideband;
broadband;
linearization;
low power;
noise and distortion cancellation;
shunt-feedback;
9.
Internet of Things: Evolution towards a hyper-connected society
机译:
物联网:向高度互联的社会的演进
作者:
Choi Alex Jinsung
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
Big Data;
Internet;
Internet of Things;
cloud computing;
computer network security;
data analysis;
data integration;
next generation networks;
reliability;
Internet;
Internet of Things;
IoT infrastructure;
big data analytics;
cloud computing;
cost-effectiveness;
hyper-connected society;
next generation network;
service reliability;
ultra-low power operation;
Business;
Cloud computing;
Intelligent sensors;
Internet of Things;
Long Term Evolution;
Security;
IoT;
big data analytics;
cloud computing;
flexiblity;
hyper-conneted society;
scalability;
security;
10.
A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput
机译:
UHS-II SD卡控制器,具有240MB / s的写入吞吐量和260MB / s的读取吞吐量
作者:
Yasufuku Kenta
;
Oshiyama Naoto
;
Saito Takashi
;
Miyamoto Yutaka
;
Nakamura Yoshihiko
;
Terauchi Ryota
;
Kondo Atsushi
;
Aoyama Tadayoshi
;
Takahashi Masaharu
;
Oowaki Yukihito
;
Bandai Ryoichi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
clock and data recovery circuits;
semiconductor storage;
CDR logic;
IO lanes;
IO pins;
SLVS-type driver;
UHS-II SD card controller;
clock data recovery logic;
double data rate;
down-streams;
loss 15 dB;
noise tolerance improvement;
read throughput;
up-streams;
write throughput;
Data transfer;
Impedance;
Noise;
Regulators;
Switches;
Throughput;
CDR;
SD cards;
UHS-II;
bidirectional;
return loss;
serial interface;
11.
A 0.43pJ/bit true random number generator
机译:
一个0.43pJ / bit真随机数发生器
作者:
Ting-Kuei Kuan
;
Yu-Hsuan Chiang
;
Shen-Iuan Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS logic circuits;
calibration;
jitter;
random number generation;
signal generators;
CMOS technology;
NIST tests;
TRNG;
bit rate 500 kbit/s;
environment variations;
jitter signal generator;
logic probability;
noise pre-amplification;
offset calibration;
power 214 nW;
size 40 nm;
small-area energy-efficient true random number generator;
voltage 0.8 V;
Calibration;
Generators;
Jitter;
Latches;
NIST;
Noise;
Signal generators;
12.
A sub-threshold to super-threshold Level Conversion Flip Flop for subear-threshold dual-supply operation
机译:
亚阈值至超阈值电平转换触发器,用于亚阈值/近阈值双电源操作
作者:
Chao Wang
;
Jun Zhou
;
Xin Liu
;
Annamalai Arasu Muthukumaraswamy
;
Minkyu Je
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
FIR filters;
current mirrors;
energy conservation;
flip-flops;
integrated circuit design;
logic design;
low-power electronics;
silicon;
CM-based MS-LCFF;
LCFF-based dual-supply operation;
Si;
current mirror;
data latching;
dual-supply designs;
energy efficiency;
frequency 300 kHz;
level shifting;
master-slave level conversion flip flop;
multisupply designs;
near-threshold dual-supply operation;
near-threshold voltage;
power consumption;
power reduction;
silicon area;
size 0.18 mum;
subthreshold FIR filter;
subthreshold dual-supply operation;
subthreshold level conversion flip flop;
subthreshold voltage;
super-threshold level conversion flip flop;
super-threshold voltage;
voltage 0.3 V to 0.5 V;
Clocks;
Delays;
Energy efficiency;
Finite impulse response filters;
Latches;
MOS devices;
Robustness;
13.
A reconfigurable analog baseband for single-chip, Saw-less, 2G/3G/4G cellular transceivers with carrier aggregation
机译:
可重配置的模拟基带,适用于具有载波聚合功能的单芯片,无锯,2G / 3G / 4G蜂窝收发器
作者:
Jongwoo Lee
;
Byungki Han
;
Jae-hyun Lim
;
Su-seob Ahn
;
Jae-kwon Kim
;
Cho Thomas
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
3G mobile communication;
4G mobile communication;
CMOS integrated circuits;
Q-factor;
cellular radio;
interference suppression;
radio transceivers;
2G transceivers;
3G transceivers;
4G transceivers;
CMOS;
DAC image suppression;
DC offset;
MIMO transceivers;
Q offset;
RX filter;
capacitor sharing technique;
carrier aggregation;
cellular transceivers;
constant envelope;
digital calibration;
frequency 0.1 MHz to 14 MHz;
gain 93 dB;
handheld products;
log tuning;
mass production;
noise suppression;
power 10.2 mW;
power 7.3 mW;
power 8.4 mW;
ramping envelope;
reconfigurable analog baseband;
saw-less;
size 65 nm;
voltage 1.2 V;
Bandwidth;
Baseband;
Capacitors;
Gain;
Passive filters;
Power harmonic filters;
Tuning;
CMOS analog filter;
logarithmic tuning resistor;
14.
A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient response
机译:
具有带宽可重新配置的电流模式降压转换器,以提高效率并改善负载瞬态响应
作者:
Pai-Yi Wang
;
Li-Te Wu
;
Tai-Haur Kuo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
current-mode circuits;
power convertors;
transient response;
CM26 process;
current 700 mA;
current-mode buck converter;
current-mode control;
efficiency 96.3 percent;
efficiency enhancement;
fast frequency;
fixed compensation coefficients;
load transient response improvement;
reconfigurable compensation coefficients;
size 0.35 mum;
slow frequency;
switched-capacitor compensator;
time 5 mus;
transient detector;
variable-frequency controllers;
voltage 75 mV;
Bandwidth;
Detectors;
Frequency control;
Pulse width modulation;
Switches;
Switching frequency;
Transient analysis;
compensator;
current mode;
dc-dc converter;
switched capacitor;
transient response;
15.
A 1V input, 3-to-6V output, integrated 58-efficient charge-pump with hybrid topology and parasitic energy collection for 66 area reduction and 11 efficiency improvement
机译:
1V输入,3至6V输出,集成了58%效率的集成集成拓扑和寄生能量收集的电荷泵,可减少66%的面积并提高11%的效率
作者:
Jen-Huan Tsai
;
Sheng-An Ko
;
Hui-Huan Wang
;
Chia-Wei Wang
;
Hsin Chen
;
Po-Chiun Huang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
MOS capacitors;
charge pump circuits;
voltage multipliers;
CMOS process;
Dickson chargepumps;
area reduction;
auxiliary charge-pumps;
auxiliary parasitic pumping paths;
cascoded doublers;
charge-pump;
current 30 muA to 40 muA;
efficiency 48 percent to 58 percent;
efficiency improvement;
efficiency loss;
efficiency performance;
feed-forward charge-pump;
hybrid topology;
internal pumping capacitors;
low-area high-efficiency hybrid 6-stage voltage multiplier;
modified Cockcroft-Walton charge-pumps;
on-chip Dickson CP;
on-chip MOS capacitors;
parasitic energy;
parasitic energy collection;
size 0.18 mum;
voltage 1 V;
voltage 3 V to 6 V;
CMOS integrated circuits;
Capacitors;
Charge pumps;
Clocks;
Stress;
Switches;
Topology;
Charge-pump;
DC-DC boost converter;
16.
A power efficient frequency shaping neural recorder with automatic bandwidth adjustment
机译:
具有自动带宽调整功能的高效功率成形神经记录仪
作者:
Jian Xu
;
Tong Wu
;
Zhi Yang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
bioelectric potentials;
biomedical electronics;
digital filters;
low-power electronics;
noise;
bandwidth 8 kHz;
capacitance 3 pF;
frequency 80 kHz;
size 0.13 mum;
voltage 1.0 V;
voltage 2.2 muV;
Bandwidth;
Capacitors;
Clocks;
Electrodes;
Impedance;
Noise cancellation;
17.
A 10.4 mW electrical impedance tomography SoC for portable real-time lung ventilation monitoring system
机译:
用于便携式实时肺通气监测系统的10.4 mW电阻抗层析成像SoC
作者:
Sunjoo Hong
;
Jaehyuk Lee
;
Joonsung Bae
;
Hoi-Jun Yoo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
biomedical electronics;
electric impedance imaging;
lung;
patient monitoring;
pneumodynamics;
portable instruments;
system-on-chip;
ADC speed;
CMOS technology;
EIT SoC;
I/Q signal generation;
T-switch;
belt-type EIT system;
dynamic lung ventilation images;
electrical impedance tomography SoC;
electrodes;
high fidelity image;
high off isolation;
mobile devices;
on-chip fast demodulation scheme;
portable real-time lung ventilation monitoring system;
power 10.4 mW;
scanning time;
voltage 1.8 V;
Electrodes;
Impedance;
Lungs;
Monitoring;
System-on-chip;
Tomography;
Ventilation;
Electrical impedance tomography;
complex impedance;
low power;
ventilation monitoring;
18.
A 0.015-mm2 60-GHz reconfigurable wake-up receiver by reusing multi-stage LNAs
机译:
通过重用多级LNA来实现0.015-mm 2 sup> 60 GHz可重配置唤醒接收机
作者:
Rui Wu
;
Qinghong Bu
;
Wei Deng
;
Okada Kenichi
;
Matsuzawa Akira
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
antennas;
detector circuits;
low noise amplifiers;
radio receivers;
CMOS process;
antennas;
bulky components;
envelope detectors;
frequency 60 GHz;
gain stages;
input matching network;
multistage LNA;
multistage low-noise amplifiers;
power 12.7 mW;
power 64 muW;
pre-amplifier;
reconfigurable wake-up receiver;
reconfiguration techniques;
sensitivity-boost mode;
size 65 nm;
Baseband;
Envelope detectors;
Logic gates;
Power demand;
Receivers;
Sensitivity;
Transceivers;
60-GHz wake-up receiver;
CMOS;
LNA-reused;
area-efficient;
19.
A 330μW, 64-channel neural recording sensor with embedded spike feature extraction and auto-calibration
机译:
具有嵌入式尖峰特征提取和自动校准功能的330μW,64通道神经记录传感器
作者:
Rodriguez-Perez Alberto
;
Delgado-Restituto Manuel
;
Darie Angela
;
Soto-Sanchez Cristina
;
Fernandez-Jover Eduardo
;
Rodriguez-Vazquez Angel
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
biomedical electronics;
biosensors;
brain;
feature extraction;
microprocessor chips;
neural chips;
prosthetics;
autocalibration mechanism;
data streams;
digital processor;
feature vectors;
in vivo measurements;
integrated neural recording sensor;
neural signals;
neural spikes;
power 330 muW;
power consumption;
spike feature extraction;
Arrays;
Calibration;
Feature extraction;
Noise;
Power demand;
Wireless communication;
Wireless sensor networks;
20.
An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI
机译:
具有1.5pJ / bit最大数字脉冲发送器和89.5μW超再生RSSI的超低功耗RF收发器
作者:
Ito H.
;
Yoneda Yoshihiro
;
Ibe Taiki
;
Hamada Takahiro
;
Ishihara Noboru
;
Masu Kazuya
;
Masui Shoichi
;
Momiyama Youichi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
RSSI;
low-power electronics;
power consumption;
radio transceivers;
sensor placement;
wireless sensor networks;
CMOS;
I-TX;
WSN application;
bit rate 10 Mbit/s;
bit-level duty cycling operation;
low-power localization;
low-rate downlink;
maximally-digital impulse-transmitter;
power 89.5 muW;
sensitivity consumption;
start-up time oscillation;
super-regenerative RSSI;
super-regenerative received-signal-strength-indicator circuit;
superior energy-per-bit;
ultra low power consumption;
ultra low-power RF transceiver;
wireless sensor network application;
Bit rate;
Power demand;
Power generation;
Power measurement;
Radio frequency;
Sensitivity;
Transceivers;
21.
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication
机译:
一个1.4M像素CMOS图像传感器,具有基于多行重新扫描的数据采样,用于光学相机通信
作者:
Deguchi J.
;
Yamagishi Tatsuya
;
Majima H.
;
Ozaki N.
;
Hiwada K.
;
Morimoto Masayuki
;
Ashitani T.
;
Kousai Shouhei
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS image sensors;
image sampling;
light emitting diodes;
optical communication;
optical modulation;
optical projectors;
optical sensors;
CIS;
CMOS image sensor;
IEEE 802.15.SG7a OCC;
MRR;
data sampling;
modulated LED spot;
multiple row-rescan;
optical camera communication;
picture size 1.4 Mpixel;
Conferences;
Solid state circuits;
CMOS image sensor;
IEEE 802.15.7 VLC;
IEEE 802.15.SG7a OCC;
multiple row-rescan;
22.
A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI
机译:
在28nm FD SOI中具有0.011 mm 2 sup> PVT稳健的完全可合成CDR,数据速率为10.05 Gb / s
作者:
Narayanan Aravind Tharayil
;
Wei Deng
;
Dongsheng Yang
;
Rui Wu
;
Okada Kenichi
;
Matsuzawa Akira
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
calibration;
clock and data recovery circuits;
network synthesis;
silicon-on-insulator;
FDSOI technology;
PVT-robust fully-synthesizable CDR;
automated place;
automated route;
background calibration mechanism;
bit rate 10.05 Gbit/s;
clock and data recovery circuit;
fully-synthesizable all-digital architecture;
high speed applications;
injection locking technique;
power 16 mW;
size 28 nm;
voltage 1.0 V;
CMOS integrated circuits;
Calibration;
Clocks;
Frequency locked loops;
Jitter;
Oscillators;
Radiation detectors;
23.
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system
机译:
2.5W平板扬声器通过基于心理声学模型的自适应功率管理系统提供3.2W伪高功率
作者:
Shin-Hao Chen
;
Shen-Yu Peng
;
Ke-Horng Chen
;
Shin-Chi Lai
;
Sheng Kang
;
Kevin Cheng
;
Ying-Hsi Lin
;
Chen-Chih Huang
;
Chao-Cheng Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
audio equipment;
automatic gain control;
digital signal processing chips;
harmonic distortion;
AGC;
APM system;
RT-DLI monitoring;
SPL;
THD;
adaptive power management system;
automatic gain control;
conventional clipping technique;
power 0.32 W;
power 2.5 W;
power 3.2 W;
psychoacoustic model;
real-time dynamic loading impedance monitoring;
sound pressure level;
speaker damage;
tablet speaker;
total-harmonic-distortion;
z-DSP;
z-domain digital signal processing;
Digital signal processing;
Impedance;
Loading;
Monitoring;
Power amplifiers;
Power generation;
Psychoacoustic models;
class D audio amplifier;
digital signal processing;
power suppression;
psychoacoustic model;
speaker protection;
24.
A 1–100Mb/s 0.5–9.9mW LDPC convolutional code decoder for body area network
机译:
用于人体局域网的1–100Mb / s 0.5–9.9mW LDPC卷积码解码器
作者:
Chih-Lung Chen
;
Sheng-Jhan Wu
;
Hsie-Chia Chang
;
Chen-Yi Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
Zigbee;
body area networks;
convolutional codes;
forward error correction;
low-power electronics;
parity check codes;
power consumption;
CMOS technology;
FEC candidate;
IEEE 802.15.4g;
IEEE 802.15.6;
Viterbi decoder;
bit rate 1 Mbit/s to 100 Mbit/s;
body area network;
error correcting performance;
forward error correction;
low power LDPC convolutional code decoder;
power 0.5 mW to 9.9 mW;
power consumption;
shift-shared memory architecture;
silicon area;
size 90 nm;
supply voltage;
voltage 0.6 V;
Convolutional codes;
Decoding;
Forward error correction;
IEEE 802.15 Standards;
Power demand;
Semiconductor device measurement;
Voltage measurement;
25.
A programmable discrete-time filter employing hardware-efficient two-dimensional implementation method
机译:
采用硬件有效二维实现方法的可编程离散时间滤波器
作者:
Jaeyoung Choi
;
Raja M. Kumarasamy
;
Arasu M. Annamalai
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
FIR filters;
discrete time filters;
programmable filters;
radio receivers;
CMOS;
FIR;
bandwidth 1.22 MHz to 1.27 MHz;
charge accumulation filters;
charge sharing filters;
frequency 100 MHz to 300 MHz;
gain 56.8 dB to 59.1 dB;
programmable discrete-time filter;
size 65 nm;
wideband wireless receivers;
Band-pass filters;
Clocks;
Finite impulse response filters;
Gain;
IIR filters;
Receivers;
Wideband;
discrete-time filter;
reconfigurable;
software-defined radio (SDR);
switched-capacitor filter;
wideband;
26.
A 0.1–5GHz flexible SDR receiver in 65nm CMOS
机译:
采用65nm CMOS的0.1-5GHz灵活SDR接收器
作者:
Xinwang Zhang
;
Yang Xu
;
Bingqiao Liu
;
Qian Yu
;
Siyang Han
;
Qiongbing Liu
;
Zehong Zhang
;
Yanqiang Gao
;
Zhihua Wang
;
Baoyong Chi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
low noise amplifiers;
operational amplifiers;
radio receivers;
sigma-delta modulation;
software radio;
CMOS;
LNA;
RF filtering;
RF front-end paths;
SDR receiver;
class-AB op-amp;
current 9.6 mA to 47.4 mA;
feed-forward compensation;
frequency 0.1 GHz to 5 GHz;
frequency 10 MHz;
harmonic interferences;
harmonic rejection;
noise figure 3.8 dB;
out-of-band blockers;
quasi-floating gate techniques;
sigma-delta ADC;
size 65 nm;
software-defined radio receiver;
voltage 1.2 V;
Calibration;
Filtering;
Harmonic analysis;
Linearity;
Power harmonic filters;
Radio frequency;
Receivers;
LNA;
Op-Amp;
Receiver;
SDR;
Sigma-Delta ADC;
27.
A 3 Gb/s 64-QAM E-band direct-conversion transmitter in 40-nm CMOS
机译:
采用40 nm CMOS的3 Gb / s 64-QAM E波段直接转换发送器
作者:
Dixian Zhao
;
Reynaert Patrick
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
calibration;
integrated circuit layout;
microwave integrated circuits;
millimetre wave filters;
quadrature amplitude modulation;
radio transmitters;
64-QAM E-band direct-conversion transmitter;
CMOS;
E-band transmitter;
bit rate 3 Gbit/s;
calibration circuits;
calibration techniques;
frequency 62.5 GHz to 85.5 GHz;
frequency 71 GHz to 76 GHz;
frequency 81 GHz to 86 GHz;
millimeter-wave poly-phase filter;
size 40 nm;
CMOS integrated circuits;
Calibration;
Modulation;
Power amplifiers;
Power measurement;
Semiconductor device measurement;
Transmitters;
CMOS;
E-band;
I/Q imbalance;
LO feed-through;
calibration;
mixer;
poly-phase filter;
power amplifier;
transmitter;
28.
A fully-integrated reconfigurable dual-band transceiver for short range wireless communication in 180nm CMOS
机译:
完全集成的可重配置双波段收发器,用于180nm CMOS中的短距离无线通信
作者:
Xiaobao Yu
;
Meng Wei
;
Yun Yin
;
Ying Song
;
Siyang Han
;
Qiongbing Liu
;
Zongming Jin
;
Xiliang Liu
;
Zhihua Wang
;
Baoyong Chi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
UHF integrated circuits;
UHF oscillators;
UHF power amplifiers;
error compensation;
phase locked loops;
power control;
radio networks;
radio transceivers;
voltage-controlled oscillators;
CMOS power amplifier;
HRR;
LO;
NF;
OP1dB;
PAE;
PLL;
RF Amplifiers;
RF front-end;
S2D RFA;
class-c VCO;
dual-band TRX;
frequency 2.4 GHz;
fully-integrated reconfigurable dual-band transceiver;
gain error compensation;
harmonic rejection ratio;
input signal PAPR detection;
multimode CMOS PA;
notch filtering;
peak-to-average-power-ratio;
phase error compensation;
power control loop;
short range wireless communication;
single-ended-to-differential RFA;
size 180 nm;
CMOS integrated circuits;
Harmonic analysis;
Impedance matching;
Power generation;
Power harmonic filters;
Radio frequency;
Transceivers;
29.
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications
机译:
适用于移动医疗应用的0.65V 1.2mW 2.4GHz / 400MHz双模相位调制器
作者:
Yang Li
;
Ni Xu
;
Yining Zhang
;
Woogeun Rhee
;
Sanghoon Kang
;
Zhihua Wang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
FIR filters;
body area networks;
mobile communication;
quadrature phase shift keying;
CMOS;
DCO nonlinearity;
FIR filter;
FIR-embedded OQPSK modulation;
digital-intensive phase modulator;
dual-mode phase modulator;
frequency 2.4 GHz;
frequency 400 MHz;
harmonic filtering technique;
mobile healthcare applications;
phase interpolator;
power 1.2 mW;
semidigital fractional-N PLL;
size 65 nm;
spectral regrowth;
voltage 0.65 V;
Finite impulse response filters;
Frequency modulation;
Inverters;
Phase locked loops;
Phase modulation;
Voltage-controlled oscillators;
30.
A 5.2mW IEEE 802.15.6 HBC standard compatible transceiver with power efficient delay-locked-loop based BPSK demodulator
机译:
具有5.2mW IEEE 802.15.6 HBC标准的兼容收发器,具有基于功率高效延迟锁定环的BPSK解调器
作者:
Hyunwoo Cho
;
Hyungwoo Lee
;
Joonsung Bae
;
Hoi-Jun Yoo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
access protocols;
active filters;
body area networks;
circuit feedback;
delay lock loops;
demodulators;
low noise amplifiers;
phase shift keying;
radio transceivers;
synchronisation;
0.13μm CMOS process;
DLL control voltage;
LNA;
MAC operation;
RSSI;
WBAN;
analog active filter;
current 4.3 mA;
energy detection ability;
human body communication;
low power fully IEEE 802.15.6 HBC standard compatible transceiver;
operating mode adjustment;
power 5.2 mW;
power efficient delay-locked-loop based BPSK demodulator;
power reduction;
received signal strength indicator detector;
sample-and-hold operation;
synchronization circuits;
synchronization feedback loop stability problem;
voltage 1.2 V;
wireless body area network;
Active filters;
Binary phase shift keying;
Demodulation;
Power demand;
Receivers;
Synchronization;
Transceivers;
31.
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor
机译:
0.4V 280nW无频率参考的几乎全数字混合域温度传感器
作者:
Wenfeng Zhao
;
Rui Pan
;
Yajun Ha
;
Zhi Yang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
temperature sensors;
CMOS process;
delay sensor;
hybrid domain all-digital processing technique;
power 280 nW;
size 65 nm;
subthreshold frequency reference less temperature sensor;
subthreshold ratioed current sensor;
temperature 0 degC to 100 degC;
voltage 0.4 V;
Delays;
Frequency-domain analysis;
MOS devices;
Power demand;
Semiconductor device measurement;
Temperature measurement;
Temperature sensors;
32.
A 3.12 pJ/bit, 19–27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery
机译:
一个3.12 pJ /位,19-27 Gbps的接收器,带有2个Tap-DFE嵌入式时钟和数据恢复
作者:
Zheng-Hao Hong
;
Wei-Zen Chen
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
clock and data recovery circuits;
decision feedback equalisers;
interference suppression;
intersymbol interference;
jitter;
receivers;
relaxation oscillators;
2 tap-DFE embedded clock and data recovery circuit;
CMOS technology;
CTLE;
ISI;
Nyquist frequency;
bit rate 19 Gbit/s to 27 Gbit/s;
broadband PLL;
channel loss compensation;
continuous time linear equalizer;
decision feedback equalizer;
high energy efficiency;
hybrid CDR;
jitter suppression;
loss 20 dB;
quadrature relaxation type oscillator;
receiver;
sampling phases;
size 40 nm;
Clocks;
Decision feedback equalizers;
Engines;
Jitter;
Least squares approximations;
Phase locked loops;
Receivers;
CDR;
CTLE;
DFE;
PLL;
33.
A low-input-swing AC-DC voltage multiplier using Schottky diodes
机译:
使用肖特基二极管的低输入摆幅AC-DC电压倍增器
作者:
Ye-Sing Luo
;
Shen-Iuan Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
Schottky diodes;
limiters;
overvoltage protection;
power conversion;
voltage multipliers;
AC-DC voltage multiplier;
CMOS technology;
PCE;
Schottky diodes;
frequency 1 MHz;
limiting circuit;
matching network;
overvoltage protection;
power conversion efficiency;
size 0.18 mum;
size 0.761 mm;
CMOS integrated circuits;
Capacitors;
Limiting;
Rectifiers;
Schottky diodes;
Solid state circuits;
Voltage measurement;
34.
A 1.44mm2 4-channel UWB beamforming receiver with Q-compensation in 65nm CMOS
机译:
在65nm CMOS中具有Q补偿的1.44mm 2 sup> 4通道UWB波束成形接收器
作者:
Lei Wang
;
Yong Lian
;
Chun-Huat Heng
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
array signal processing;
buffer circuits;
low noise amplifiers;
power consumption;
radio receivers;
ultra wideband technology;
CMOS;
LC delay;
LNA;
Q-compensation;
UWB beamformer;
UWB beamforming receiver;
buffers;
low noise amplifiers;
power 288 mW;
power consumption;
size 65 nm;
time 224 ps;
time 7 ps;
Array signal processing;
Delays;
Inductors;
Receivers;
Spatial resolution;
Transmitters;
Ultra wideband technology;
UWB beamforming receiver;
current reuse LNA;
current reuse buffer;
noise cancelling LNA;
wideband phase shifter;
35.
A DC-46Gb/s 2:1 multiplexer and source-series terminated driver in 20nm CMOS technology
机译:
采用20nm CMOS技术的DC-46Gb / s 2:1多路复用器和源系列端接驱动器
作者:
Jian Hong Jiang
;
Parikh Samir
;
Lionbarger Mark
;
Nedovic Nikola
;
Yamamoto Takayuki
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
driver circuits;
logic gates;
multiplexing equipment;
power consumption;
CMOS circuit;
CMOS technology;
T-coil;
bit rate 46 Gbit/s;
bit rate 50 Gbit/s;
high speed chip-to-chip communications;
logic gates;
multiplexer;
on-chip passive devices;
peak-to-peak differential voltage swing;
power 38.7 mW;
power consumption;
series-connected on-chip resistor;
size 20 nm;
source-series terminated driver;
transmitter driver;
CMOS integrated circuits;
CMOS technology;
Jitter;
Loss measurement;
Multiplexing;
Resistors;
Transmitters;
CMOS;
T-coil;
multiplexer;
push-pull;
source-series terminated driver;
termination;
transmitter;
36.
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
机译:
2×25 Gb / s时钟和具有背景幅度锁定环路的数据恢复
作者:
Chien-Kai Kao
;
Kuan-Lin Fu
;
Shen-Iuan Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS logic circuits;
clock and data recovery circuits;
flip-flops;
CMOS process;
amplitude variation reduction;
background amplitude-locked loop;
bit rate 25 Gbit/s;
charge-steering-logic return-to-zero latch;
clock and data recovery circuit;
size 40 nm;
time 2.26 ps;
voltage 1.15 V;
Capacitors;
Clocks;
Jitter;
Latches;
Resistance;
Semiconductor device measurement;
Voltage-controlled oscillators;
37.
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor
机译:
用于移动增强现实处理器的27mW可重新配置的无标记对数相机姿态估计引擎
作者:
Injoon Hong
;
Gyeonghoon Kim
;
Youchang Kim
;
Donghyun Kim
;
Byeong-Gyu Nam
;
Hoi-Jun Yoo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
augmented reality;
mobile computing;
parallel programming;
pose estimation;
AR;
CPEE;
LPE;
RDL;
SE;
logarithmic processing element;
marker-less camera pose estimation engine;
mobile augmented reality;
reconfigurable data-arrangement layer;
reconfigurable logarithmic processor;
speculative execution;
Cameras;
Estimation;
Instruction sets;
Jacobian matrices;
Mobile communication;
Power demand;
Three-dimensional displays;
38.
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS
机译:
采用0.18μmCMOS的0.3V 10位7.3fJ /转换步SAR ADC
作者:
Cheng-En Hsieh
;
Shen-Iuan Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
comparators (circuits);
semiconductor switches;
CMOS process;
analog-to-digital converter;
conversion time;
conversion-step SAR ADC;
differential dynamic switches;
digital-to-analog converter;
double-boosted sampling switch;
figure-of-merit;
power 15.9 nW;
rail-to-rail successive approximation register;
size 0.18 mum;
splitting capacitors;
supply-boosted time-domain comparator;
voltage 0.3 V;
word length 10 bit;
CMOS integrated circuits;
Capacitors;
Solid state circuits;
Switches;
Switching circuits;
Time-domain analysis;
39.
A 10μA on-chip electrochemical impedance spectroscopy system for wearables/implantables
机译:
用于可穿戴设备/可植入设备的10μA片上电化学阻抗谱系统
作者:
Jingren Gu
;
Huanfen Yao
;
Keping Wang
;
Parviz Babak
;
Otis Brian
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
digital-analogue conversion;
electrochemical impedance spectroscopy;
filters;
harmonic generation;
integrated circuit testing;
prosthetics;
switched capacitor networks;
time-domain analysis;
CMOS process;
EIS system;
SAR ADC;
analog filter;
current 10 muA;
harmonic generation;
implantables;
on-chip electrochemical impedance spectroscopy system;
quadrature sinusoid stimulus;
response current;
sinusoid DAC;
size 1 mm;
size 1.1 mm;
size 130 nm;
switched capacitor integrator;
time-domain integration method;
voltage 1.2 V;
wearables;
Capacitors;
Electrochemical impedance spectroscopy;
Harmonic analysis;
Impedance;
Power harmonic filters;
Synchronization;
Time-domain analysis;
Electrochemical Impedance Spectroscopy;
sinusoid DAC;
time-domain integration;
40.
A 0.022mm2 98.5dB SNDR hybrid audio delta-sigma modulator with digital ELD compensation in 28nm CMOS
机译:
在28nm CMOS中具有数字ELD补偿的0.022mm 2 sup> 98.5dB SNDR混合音频delta-sigma调制器
作者:
Tze-Chien Wang
;
Yu-Hsin Lin
;
Chun-Cheng Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
asynchronous circuits;
audio signal processing;
compensation;
delay filters;
delta-sigma modulation;
digital filters;
flicker noise;
quantisation (signal);
1st-order analog filter;
1st-order digital filter;
ASAR quantizer;
CMOS process;
R-DAC;
SNDR hybrid audio delta-sigma modulator;
analog ELD feedback DAC;
area reduction;
area-efficient hybrid ΔΣ modulator;
bandwidth 24 kHz;
digital ELD compensation;
digital excess loop delay compensation;
digital signal processing;
flicker noise;
second analog integrator;
shared asynchronous successive approximation register;
size 28 nm;
word length 6 bit;
CMOS integrated circuits;
Clocks;
Delays;
Digital filters;
Modulation;
Signal to noise ratio;
41.
A 3.3V 15.6b 6.1pJ/0.02RH with 10ms response humidity sensor for respiratory monitoring
机译:
具有10ms响应湿度传感器的3.3V 15.6b 6.1pJ / 0.02%RH用于呼吸监测
作者:
Lai Kelvin Yi-Tse
;
Yu-Tao Yang
;
Bang-Jing Chen
;
Chun-Jen Shen
;
Ming-Feng Shiu
;
Zih-Cheng He
;
Hsie-Chia Chang
;
Chen-Yi Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
biomedical transducers;
health care;
humidity measurement;
humidity sensors;
microsensors;
patient monitoring;
readout electronics;
PVT variation;
TSMC CMOS MEMS process;
differential CMOS-MEMS humidity device;
energy conversion;
energy-efficient humidity sensor;
environment detection;
event-driven humidity sensor;
healthcare monitoring;
proportion-based capacitance-to-digit readout circuit;
size 0.35 mum;
time 10 ms;
voltage 3.3 V;
wearable respiratory monitoring;
word length 15.6 bit;
Capacitance;
Humidity;
Micromechanical devices;
Monitoring;
Sensitivity;
Sensors;
Time factors;
Capacitive Sensing;
Health-Care;
Humidity Sensor;
Low Energy;
Low Power;
Respiratory Monitoring;
42.
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit
机译:
6 Gb / s自适应环路带宽时钟和数据恢复(CDR)电路
作者:
Li-Hung Chiueh
;
Tai-Cheng Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
clock and data recovery circuits;
jitter;
network synthesis;
CDR loop bandwidth;
PLD;
adaptive block;
adaptive-loop-bandwidth clock and data recovery circuit;
bit rate 6 Gbit/s;
jitter spectral profile;
jitter suppression ability;
power 86.4 mW;
preventional lock detector;
sinusoidal jitter source;
Bandwidth;
Clocks;
Detectors;
Jitter;
Noise;
Tracking loops;
Voltage-controlled oscillators;
adaptive loop bandwidth;
jitter suppression;
jitter tolerance;
43.
A frequency-reconfigurable multi-standard 65nm CMOS digital transmitter with LTCC interposers
机译:
具有LTCC插入器的可重新配置频率的多标准65nm CMOS数字发射机
作者:
Nai-Chung Kuo
;
Bonjern Yang
;
Chaoying Wu
;
Lingkai Kong
;
Wang Aiping
;
Reiha Michael
;
Alon Elad
;
Niknejad Ali M.
;
Nikolic B.
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
UHF integrated circuits;
amplitude modulation;
ceramics;
cryogenic electronics;
flip-chip devices;
integrated circuit interconnections;
interpolation;
transmitters;
LTCC interposers;
PA output balun;
amplitude modulation;
carrier frequency reconfiguration;
core transmitter;
digital polar transmitter;
efficiency 52 percent;
flip-chip interconnection;
frequency 0.6 GHz to 2.4 GHz;
frequency-reconfigurable multistandard CMOS;
low-temperature cofired ceramic interposers;
operating frequency bands;
phase interpolation;
polar transmitter;
power amplifier;
size 65 nm;
universal digital modulator;
word length 8 bit;
word length 9 bit;
CMOS integrated circuits;
Frequency modulation;
Impedance matching;
OFDM;
Phase modulation;
Power amplifiers;
Transmitters;
CMOS;
LTCC;
digital polar modulation;
digital transmitter;
power amplifier;
44.
A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration
机译:
一个0.1–1.5GHz谐波抑制接收器前端,具有混合8相LO发生器,相位歧义校正和矢量增益校准
作者:
Xinwang Zhang
;
Zhihua Wang
;
Baoyong Chi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
UHF integrated circuits;
UHF mixers;
frequency synthesizers;
quadrature amplitude modulation;
radio receivers;
CMOS;
LO generator;
QAM modulation signal;
current 5.4 mA to 24.5 mA;
frequency 0.1 GHz to 1.5 GHz;
frequency synthesizer;
gain 85 dB;
harmonic rejection receiver;
local oscillating generator;
phase ambiguity correction;
phase mismatch;
size 1.8 mm;
size 65 nm;
vector gain calibration;
voltage 1.2 V;
Calibration;
Frequency measurement;
Gain;
Harmonic analysis;
Mixers;
Power harmonic filters;
Receivers;
LO generator;
harmonic rejection;
opamp;
phase ambiguity;
receiver;
45.
A 0.5-V sub-μW/channel neural recording IC with delta-modulation-based spike detection
机译:
具有基于增量调制的尖峰检测的0.5V亚μW/通道神经记录IC
作者:
Seong-Jin Kim
;
Lei Liu
;
Lei Yao
;
Wang Ling Goh
;
Yuan Gao
;
Minkyu Je
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue storage;
bioelectric potentials;
biomedical electronics;
delta modulation;
neural chips;
CMOS technology;
analog memory;
channel neural recording IC;
delta modulator;
delta-modulation-based spike detection;
power 0.88 muW;
power dissipation;
size 0.18 mum;
voltage 0.5 V;
Detectors;
Dynamic range;
Feature extraction;
Frequency modulation;
Integrated circuits;
Solid state circuits;
analog memory;
delta modulator;
low power;
low voltage;
neural recording;
spike detection;
46.
A 12-V charge pump-based square wave driver in 65-nm CMOS technology
机译:
基于65V CMOS技术的基于12V电荷泵的方波驱动器
作者:
Ismail Yousr
;
Yang Chih-Kong Ken
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
charge pump circuits;
driver circuits;
nanotechnology;
square-wave generators;
switched capacitor networks;
charge pump-based square wave driver;
nanometer-scale CMOS technology;
pulse drive;
resistance 3.7 kohm;
size 0.06 mm;
size 65 nm;
switched capacitor;
voltage 12 V;
voltage conversion;
CMOS integrated circuits;
Capacitors;
Charge pumps;
Clocks;
Logic gates;
Resistance;
Transistors;
Charge pumps;
driver circuits;
high-voltage techniques;
transistor stacking;
47.
A 44.9 PAE digitally-assisted linear power amplifier in 40 nm CMOS
机译:
采用40 nm CMOS的44.9%PAE数字辅助线性功率放大器
作者:
Haoyu Qian
;
Silva-Martinez Jose
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
UHF power amplifiers;
compensation;
power consumption;
ACLR;
CMOS process;
PA architecture;
PA power consumption;
PAE digitally-assisted linear power amplifier;
PBO;
adjacent channel leakage ratio;
baseband WCDMA signal;
binary power gain variations;
digital gain compensation;
digital predistortion technique;
efficiency 44.9 percent;
fast switching scheme;
frequency 1.9 GHz;
gain 38 dB;
input signal;
power added efficiency;
power back-off region;
power transistor segmentation;
signal power;
size 40 nm;
Baseband;
CMOS integrated circuits;
Gain;
Power generation;
Radio frequency;
Switches;
Transistors;
48.
A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting
机译:
使用边缘计数的5–20 Gb / s功率可扩展自适应线性均衡器
作者:
Yuan-Fu Lin
;
Chang-Cheng Huang
;
Lee Jiunn-Yih Max
;
Chih-Tien Chang
;
Shen-Iuan Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
adaptive equalisers;
clocks;
error statistics;
BER;
CMOS technology;
CTLE;
asynchronous clock;
bit error rates;
bit rate 5 Gbit/s to 20 Gbit/s;
edge counting technique;
power efficiency improvement;
power scalable adaptive continuous-time linear equalizer;
size 40 nm;
Adaptive equalizers;
CMOS integrated circuits;
Semiconductor device measurement;
Solid state circuits;
Threshold voltage;
Timing;
49.
A 23mW/lane 1.2–6.8Gb/s multi-standard transceiver in 28nm CMOS
机译:
采用28nm CMOS的23mW / lane 1.2–6.8Gb / s多标准收发器
作者:
Seong-Ho Lee
;
Tran Duke
;
Ali Tamer
;
Catli Burak
;
Heng Zhang
;
Wei Zhang
;
Abdul-Latif Mohammed
;
Zhi Huang
;
Guansheng Li
;
Ahmadi Mahmoud Reza
;
Momtaz Afshin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
low-power electronics;
phase locked loops;
radio transceivers;
CMOS technology;
PCIE;
PLL;
QSGMII;
RXAUI;
SATA;
SGMII;
USB3;
XAUI;
bit rate 1.2 Gbit/s to 6.8 Gbit/s;
circuit technique;
communication standards;
low-power multistandard transceiver design;
power 23 mW;
power consumption;
single-lane transceiver;
voltage 0.9 V;
CMOS integrated circuits;
Clocks;
Jitter;
Phase locked loops;
Receivers;
Standards;
Transceivers;
clock and data recovery;
high speed integrated circuits;
serializer-deserializers;
transceivers;
50.
A power management unit integrated ADSL/ADSL2+ CPE analog front-end with −93.5dB THD for DMT-based applications
机译:
一个电源管理单元,集成了具有-93.5dB THD的ADSL / ADSL2 + CPE模拟前端,用于基于DMT的应用
作者:
Yu-Kai Chou
;
Yue Feng
;
Yu-Hsin Lin
;
Cong Liu
;
Chen-Yen Ho
;
Bo Hu
;
Jun Zha
;
Chuang Steven
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
analogue-digital conversion;
digital subscriber lines;
harmonic distortion;
modems;
power consumption;
transceivers;
ADSL/ADSL2+ CPE analog front-end;
CMOS;
CTSDM ADC;
DMT;
THD;
bit rate 27.2 Mbit/s;
digital circuits;
front-end filters;
modem;
power 590 mW;
power consumption;
power management unit;
size 0.11 mum;
size 55 nm;
voltage 3.3 V;
voltage 5 V;
ADC;
ADSL;
AFE;
DAC;
DMT;
Filter;
PMU;
51.
A 20V-compliance implantable neural stimulator IC with closed-loop power control, active charge balancing, and electrode impedance check
机译:
具有闭环功率控制,有源电荷平衡和电极阻抗检查功能的20V兼容植入式神经刺激器IC
作者:
Lei Yao
;
Jianming Zhao
;
Peng Li
;
Rui-Feng Xue
;
Yong Ping Xu
;
Minkyu Je
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
bioelectric potentials;
biomedical electronics;
closed loop systems;
inductive power transmission;
neural chips;
power control;
prosthetics;
ASK;
CMOS process;
LDMOS;
LSK;
active charge balancing;
backward data transmission;
bidirectional telemetry;
closed-loop power control;
current 1.24 mA;
electrode impedance;
forward command transmission;
frequency 13.56 MHz;
inductively powered implantable neural stimulator IC;
size 0.18 mum;
size 2 mm;
voltage 20 V;
voltage 24 V;
voltage 50 mV;
Amplitude shift keying;
Coils;
Electrodes;
Impedance;
Integrated circuits;
Power control;
Solid state circuits;
Neural stimulator;
active charge balancing;
closed-loop power control;
electrode impedance check;
high-compliance-voltage;
implantable;
52.
A nonvolatile look-up table using ReRAM for reconfigurable logic
机译:
使用ReRAM进行可重新配置逻辑的非易失性查找表
作者:
Wen-Pin Lin
;
Shyh-Shyuan Sheu
;
Chia-Chen Kuo
;
Pei-Ling Tseng
;
Meng-Fan Chang
;
Keng-Li Su
;
Chih-Sheng Lin
;
Kan-Hsueh Tsai
;
Sih-Han Lee
;
Szu-Chieh Liu
;
Yu-Sheng Chen
;
Heng-Yuan Lee
;
Ching-Chih Hsu
;
Chen F.T.
;
Tzu-Kun Ku
;
Ming-Jinn Tsai
;
Ming-Jer Kao
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
resistive RAM;
table lookup;
CMOS;
SRAM-MRAM-hybrid LUT;
complementary metal-oxide semiconductor;
instant-on functions;
magnetoresistive random-access memory;
nonvolatile look-up table;
normally-off functions;
nvLUT;
reconfigurable logic;
resistive random access memory cells;
size 0.18 mum;
standby current suppression;
static random access memory;
three-input ReRAM;
time 900 ps;
two-input ReRAM;
Adders;
Delays;
Hafnium compounds;
Nonvolatile memory;
Phase change random access memory;
Table lookup;
FPGA;
LUT;
Look-Up Table;
RRAM;
ReRAM;
nonvolatile logic;
resistive memory;
53.
A 16.6μW 32.8MHz monolithic CMOS relaxation oscillator
机译:
一个16.6μW32.8MHz单片CMOS弛豫振荡器
作者:
Yat-Hei Lam
;
Seong-Jin Kim
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
closed loop systems;
low-power electronics;
relaxation oscillators;
CCDC;
CMOS process;
CVS threshold voltage;
Gm-C error integrator;
comparator-free switch logic block;
current-controlled delay cell;
cycle-to-cycle capacitor voltage swing;
frequency 32.8 MHz;
line sensitivity;
logic supply regulator;
low power supply insensitive monolithic CMOS relaxation oscillator;
low-power closed-loop control;
power 16.6 muW;
size 0.18 mum;
switching-losses reduction;
temperature 293 K to 298 K;
voltage 1.5 V to 3.6 V;
voltage-mode comparators;
CMOS integrated circuits;
Capacitors;
Delays;
Oscillators;
Regulators;
Switches;
Temperature measurement;
Capacitor Voltage Swing;
Clock Generator;
Delay-Cell;
FOM;
Low-power;
Power Efficiency;
Relaxation oscillator;
54.
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing
机译:
具有自适应对准注入时序的新型2.4至3.6 GHz宽带亚谐波注入锁定PLL
作者:
Zhao Zhang
;
Liyuan Liu
;
Nanjian Wu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
UHF integrated circuits;
field effect MMIC;
phase locked loops;
phase noise;
1P9M CMOS process;
SILPLL;
adaptively-aligned injection timing technique;
frequency 2.4 GHz to 3.6 GHz;
half-integral injection;
output clock frequency;
output frequency resolution;
phase-noise;
power 9.1 mW;
pulse generator;
size 65 nm;
time 146 fs;
voltage 1.2 V;
wideband subharmonically injection-locked PLL;
Clocks;
Frequency measurement;
Injection-locked oscillators;
Phase locked loops;
Timing;
Voltage-controlled oscillators;
Wideband;
Low jitter;
adaptively-aligned;
half-integral injection;
injection timing;
subharmonically injection-locked PLL (SILPLL);
wideband;
55.
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor
机译:
非对称锁频环(AFLL),用于在28nm SPARC M6处理器中生成自适应时钟
作者:
Yifan YangGong
;
Turullols Sebastian
;
Woo Dong-Gyun
;
Changku Huang
;
King Yen
;
Krishnaswamy Venkatesh
;
Holdbrook Kalon
;
Shin Jinuk Luke
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
frequency locked loops;
oscillators;
AFLL;
CMOS process;
DCO;
SPARC M6 processor features;
adaptive clock generation;
asymmetric frequency locked loop;
improved noise immunity;
on-chip Ldi-dt noise;
power 14 mW;
size 28 nm;
voltage noise;
Calibration;
Clocks;
Frequency locked loops;
Frequency modulation;
Logic gates;
Noise;
System-on-chip;
56.
A 50-Gb/s differential transimpedance amplifier in 65nm CMOS technology
机译:
采用65nm CMOS技术的50 Gb / s差分跨阻放大器
作者:
Sang Gyun Kim
;
Seung Hwan Jung
;
Yun Seong Eo
;
Seung Hoon Kim
;
Xiao Ying
;
Hanbyul Choi
;
Chaerin Hong
;
Kyungmin Lee
;
Sung Min Park
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
differential amplifiers;
feedback amplifiers;
operational amplifiers;
asymmetric transformer peaking technique;
bandwidth 50 GHz;
bandwidth extension;
bit rate 50 Gbit/s;
capacitance 50 fF;
differential signaling;
differential transimpedance amplifier;
modified regulated-cascode input stage;
photodiode capacitance;
power 49.2 mW;
shunt-feedback common-source amplifier;
size 65 nm;
standard CMOS process;
transimpedance gain;
voltage 1.2 V;
Bandwidth;
CMOS integrated circuits;
CMOS technology;
Current measurement;
Optical receivers;
Semiconductor device measurement;
Sensitivity;
CMOS;
TIA;
regulated-cascode;
transformer;
57.
A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS
机译:
65nm CMOS中的3MHz至1.8GHz94μW至9.5mW 0.0153mm 2 sup>全数字延迟锁定环路
作者:
Chun-Yuan Cheng
;
Jinn-Shyan Wang
;
Pei-Yuan Chou
;
Shiou-Ching Chen
;
Chi-Tien Sun
;
Yuan-Hua Chu
;
Tzu-Yi Yang
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
clocks;
delay lock loops;
integrated circuit design;
low-power electronics;
power consumption;
CMOS;
all-digital delay-locked loop;
automatic bypassing;
clock frequency;
clock gating;
closed-loop ADDLL;
coarse locking;
cyclic delay deduction;
cyclic half-delay-line architecture;
frequency 3 MHz to 1.8 GHz;
power 94 muW to 9.5 mW;
power consumption;
size 0.0153 mm;
size 65 nm;
CMOS integrated circuits;
Clocks;
Delay lines;
Delays;
Jitter;
Power demand;
Radiation detectors;
ADDLL;
low power;
small area;
wide range;
58.
A 10b 100kS/s SAR ADC with charge recycling switching method
机译:
具有电荷回收切换方法的10b 100kS / s SAR ADC
作者:
Kai-Hsiang Chiang
;
Soon-Jyh Chang
;
Guan-Ying Huang
;
Ying-Zu Lin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
Nyquist criterion;
analogue-digital conversion;
comparators (circuits);
switching convertors;
CMOS;
FoM;
Nyquist rate;
SAR ADC;
charge recycling switching method;
figure-of-merit;
power 107 nW;
power dissipation;
size 90 nm;
switching energy;
voltage 0.4 V;
window-based reconfigurable comparator;
CMOS integrated circuits;
Capacitors;
Linearity;
Power demand;
Recycling;
Signal to noise ratio;
Switches;
59.
A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier
机译:
使用动态放大器的0.5至1 V 9位15至90 MS / s数字内插流水线SAR ADC
作者:
Lin James
;
Xu Zongben
;
Miyahara Masaya
;
Matsuzawa Akira
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
amplifiers;
analogue-digital conversion;
interpolation;
CMOS;
digital interpolation;
digitally interpolated pipelined-SAR ADC;
gain variation;
interstage gain requirement;
open-loop dynamic amplifier;
power 0.48 mW;
residue amplifier;
size 65 nm;
supply voltage scaling;
voltage 0.5 V to 1 V;
word length 9 bit;
CMOS integrated circuits;
Clocks;
Gain;
Interpolation;
Power demand;
Prototypes;
Robustness;
60.
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel
机译:
一个16.8Gbps /通道的65nm CMOS单通道收发器,用于Si载波通道上基于SiP的DRAM接口
作者:
Hyunbae Lee
;
Taeksang Song
;
Sangyeon Byeon
;
Kwanghun Lee
;
Inhwa Jung
;
Seongjin Kang
;
Ohkyu Kwon
;
Koeun Cheon
;
Donghwan Seol
;
Jongho Kang
;
Gunwoo Park
;
Yunsaing Kim
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
DRAM chips;
equalisers;
system-in-package;
transceivers;
CMOS;
DRAM interface;
SiP;
bit rate 16.8 Gbit/s;
continuous time linear equalizer;
feed forward equalizer;
multiplexer;
silicon carrier channel;
single ended signaling;
single ended transceiver;
size 65 nm;
source follower;
Bit error rate;
CMOS integrated circuits;
Random access memory;
Receivers;
Sensors;
Silicon;
Transceivers;
BER and 120Ω terminations;
CTLE;
FFE;
Self Vref Generator;
SiP based DRAM Interface;
Single Ended Transceiver;
61.
A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS
机译:
具有恒定负电平写驱动器的可配置2合1 SRAM编译器,用于16nm Fin-FET CMOS中的低Vmin
作者:
Ching-Wei Wu
;
Ming-Hung Chang
;
Chia-Cheng Chen
;
Lee Razak
;
Hung-Jen Liao
;
Chang Joana
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS memory circuits;
MOSFET circuits;
SRAM chips;
driver circuits;
6T-SRAM cell;
CNL-WD;
FinFET CMOS technology;
P2P-SRAM function;
SP-SRAM function;
area-free constant-negative-level write driver;
configurable 2-in-1 SRAM compiler;
dynamic read-or-write-first selection;
low voltage operation;
pseudotwo-port SRAM function;
read-first pseudotwo-port SRAM design;
single-port SRAM function;
size 16 nm;
write-through function;
Arrays;
CMOS integrated circuits;
Capacitors;
Clocks;
SRAM cells;
Voltage measurement;
compiler;
configurable;
low Vmin;
negative-level;
pseudo two-port SRAM;
62.
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS
机译:
用于100 GBE的110 mW 6位36 GS / s交错SAR ADC,在32 nm SOI CMOS中占0.048 mm 2 sup>
作者:
Kull Lukas
;
Pliva Jan
;
Toifl Thomas
;
Schmatz Martin
;
Francese Pier Andrea
;
Menolfi Christian
;
Braendli Matthias
;
Kossel Marcel
;
Morf Thomas
;
Andersen Toke Meyer
;
Leblebici Yusuf
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
silicon-on-insulator;
2-channel interleaver;
SOI CMOS;
area-optimized clocked reference buffer;
bandwidth enhancement;
data demultiplexing;
power 110 mW;
power-optimized asynchronous interleaved ADC SAR;
size 32 nm;
tunable constant-current source;
voltage 0.9 V;
voltage 1 V;
word length 6 bit;
Bandwidth;
CMOS integrated circuits;
Capacitors;
Delays;
Power demand;
Signal to noise ratio;
Switches;
63.
A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration
机译:
使用可控制的RZ窗口,0.11μmCMOS的12位250 MS / s 28 mW +70 dB SFDR DAC,用于无线SoC集成
作者:
Seonggeon Kim
;
Jaehyun Kang
;
Minjae Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
digital-analogue conversion;
integrated circuit design;
power amplifiers;
power consumption;
radio transmitters;
system-on-chip;
CMOS technology;
ET power amplifier;
IQ baseband wireless transmitter;
Nyquist bandwidth;
SFDR DAC;
clock duty cycle;
code-dependent transient;
common-mode controls;
controllable RZ window;
current-steering digital-to-analog converter;
envelop tracking;
flexible swing;
half clock period return-to-zero;
power 28 mW;
power consumption;
signal loss;
size 0.11 mum;
size 0.117 mm;
spurious-free dynamic range;
voltage 2.5 V;
wireless SoC integration;
CMOS integrated circuits;
Clocks;
Delays;
Flip-flops;
MOS devices;
System-on-chip;
Transient analysis;
Current-steering;
cascode;
digital-to-analog converter (DAC);
dynamic element matching (DEM);
return-to-zero (RZ);
spurious-free dynamic range (SFDR);
64.
A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS
机译:
40 nm CMOS中的2×20 Gb / s,1.2 pJ / bit,时间交错光接收器
作者:
Shih-Hao Huang
;
Zheng-Hao Hung
;
Wei-Zen Chen
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
demultiplexing equipment;
optical receivers;
photodetectors;
ALPD current-sensing scheme;
alternating photodetector current-sensing scheme;
bit rate 20 Gbit/s;
bulk CMOS technology;
correlation-based timing recovery;
demultiplexer;
digital comparator;
front-end receiver;
single-chip time-interleaved integrating-type optical receiver;
size 40 nm;
CMOS integrated circuits;
Capacitors;
Optical receivers;
Partial discharges;
Sensitivity;
Timing;
Monolithic optical receiver;
comparator;
high-density optical interconnect;
photodetector (PD);
65.
A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET
机译:
具有动态阈值MOSFET的0.52V 5.7GHz低噪声子采样PLL
作者:
Ikeda Shoji
;
Sang-yeop Lee
;
Ito H.
;
Ishihara Noboru
;
Masu Kazuya
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
charge pump circuits;
field effect transistor switches;
phase detectors;
phase locked loops;
DTMOS switch;
SSPD;
dynamic threshold MOSFET;
frequency 5.71 GHz;
frequency-locked loop;
low noise subsampling PLL;
low voltage subsampling PLL;
power 1.72 mW;
signal attenuation;
size 65 nm;
subsampling charge pump;
subsampling phase detector;
voltage 0.52 V;
Frequency locked loops;
Phase locked loops;
Phase noise;
Power demand;
Switches;
Voltage-controlled oscillators;
66.
A 135-μW 0.46-mΩ/√Hz thoracic impedance variance monitor with square-wave current modulation
机译:
具有方波电流调制的135μW0.46-mΩ/√Hz胸阻抗变化监测器
作者:
Chih-Chan Tu
;
Feng-Wen Lee
;
Dong-Feng Yeih
;
Tsung-Hsien Lin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
biomedical electronics;
electric impedance imaging;
low-power electronics;
modulation;
CMOS;
TIV information;
current 75 muA;
delayed-sampling technique;
gain-error issue;
low-power high-resolution TIV monitoring circuit;
low-power high-resolution thoracic impedance variance monitoring;
power 135 muW;
size 0.18 mum;
square-wave modulated current;
voltage 1.8 V;
Current measurement;
Demodulation;
Immune system;
Impedance;
Monitoring;
Noise;
67.
A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS
机译:
适用于20纳米CMOS的IEEE 802.11ac应用的10位320-MS / s低成本SAR ADC
作者:
Chun-Cheng Liu
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
analogue-digital conversion;
wireless LAN;
CMOS process;
ENOB;
FOM;
IEEE 802.11ac applications;
binary-scaled recombination weighting method;
low-cost SAR ADC design;
size 20 nm;
voltage 0.9 V;
voltage 1.0 V;
word length 10 bit;
Arrays;
CMOS integrated circuits;
Capacitors;
Frequency measurement;
IEEE 802.11 Standards;
Layout;
Wireless LAN;
20nm CMOS;
IEEE 802.11ac;
SAR ADC;
68.
22.5 dB open-loop gain, 31 kHz GBW pseudo-CMOS based operational amplifier with a-IGZO TFTs on a flexible film
机译:
22.5 dB开环增益,基于31 kHz GBW伪CMOS的运算放大器,在柔性薄膜上具有a-IGZO TFT
作者:
Ishida K.
;
Shabanpour R.
;
Boroujeni Bahman K.
;
Meister T.
;
Carta C.
;
Ellinger F.
;
Petti L.
;
Munzenrieder Niko S.
;
Salvatore G.A.
;
Troster G.
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
MOSFET;
flexible electronics;
operational amplifiers;
IGZO TFT;
bandwidth 31 kHz;
bandwidth 5.6 kHz;
capacitance 15 pF;
common mode feedback schemes;
cross-coupled connection;
flexible film;
gain 22.5 dB;
metal-oxide TFT technology;
nMOS transistors;
operational amplifier;
power 160 muW;
pseudo-CMOS blocks;
voltage 5 V;
Bandwidth;
CMOS integrated circuits;
Gain;
Inverters;
MOSFET;
Operational amplifiers;
Thin film transistors;
Flexible;
a-IGZO TFT;
active load;
low power;
operational amplifier;
69.
A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback
机译:
具有数字ELD补偿和多位FIR反馈的1 V 59 fJ / Step 15 MHz BW 74 dB SNDR连续时间ΔΣ调制器
作者:
Yi Zhang
;
Chia-Hung Chen
;
Tao He
;
Xin Meng
;
Qian Nancy
;
Liu Erwu
;
Elliott Phillip
;
Temes Gabor C.
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
FIR filters;
UHF filters;
array signal processing;
circuit feedback;
clocks;
compensation;
continuous time filters;
delays;
digital control;
digital-analogue conversion;
jitter;
matrix algebra;
modulators;
sensitivity analysis;
3-tap FIR feedback DAC;
3rd-order continuous-time modulator;
BW;
CMOS process;
SNDR continuous-time modulator;
bandwidth 15 MHz;
clock jitter;
core modulator;
digital ELD compensation;
digitally controlled reference switching matrix;
error signal reduction;
frequency 1.2 GHz;
highly-digital excess loop delay compensation;
loop filter linearity enhancement;
lower sensitivity;
multibit FIR feedback;
power-hungry adder;
signal bandwidth;
size 65 nm;
ultrasound beamformer;
voltage 1 V;
Clocks;
Delays;
Finite impulse response filters;
Jitter;
Modulation;
Resistors;
Switches;
70.
A 6-bit drift-resilient readout scheme for multi-level Phase-Change Memory
机译:
用于多级相变存储器的6位漂移弹性读出方案
作者:
Athmanathan Aravinthan
;
Stanisavljevic Milos
;
Cheon Jaeseung
;
Kang Sook-Yang
;
Ahn Choon Ki
;
Yoon Jinsu
;
Shin M.
;
Kim T.
;
Papandreou Nikolaos
;
Pozidis Haris
;
Eleftheriou Evangelos
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
integrated circuit design;
integrated circuit manufacture;
logic design;
phase change memories;
readout electronics;
CMOS;
drift resilience;
drift-resilient readout scheme;
multiple-level cell storage;
non volatile memory;
phase-change memory;
readout circuit;
size 64 nm;
time 450 ns;
word length 6 bit;
Computer architecture;
Measurement;
Microprocessors;
Phase change materials;
Phase change memory;
Resistance;
Voltage control;
71.
A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C
机译:
嵌入式CMOS热敏电阻的连续时间Δ-Σ温度传感器,分辨率为0.01°C
作者:
Chan-Hsiang Weng
;
Chun-Kuan Wu
;
Tsung-Hsien Lin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
delta-sigma modulation;
temperature sensors;
thermistors;
CMOS thermistor;
CTDSM;
continuous-time delta-sigma temperature sensor;
resistor-based temperature sensing module;
resistor-ladder trimming;
size 0.18 mum;
temperature 0.01 degC;
thermistor-embedded continuous-time delta-sigma modulator;
time 100 mus;
Modulation;
Noise;
Resistors;
Temperature distribution;
Temperature measurement;
Temperature sensors;
72.
An area-efficient capacitively-coupled instrumentation amplifier with a duty-cycled Gm-C DC servo loop in 0.18-μm CMOS
机译:
面积有效的电容耦合仪表放大器,具有0.18μmCMOS占空比的Gm-C直流伺服环路
作者:
Chih-Chan Tu
;
Feng-Wen Lee
;
Tsung-Hsien Lin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
bioelectric potentials;
instrumentation amplifiers;
CMOS integrated circuit;
DC servo loop;
area efficient capacitively coupled instrumentation amplifier;
biopotential signal acquisition;
chopped capacitively coupled instrumentation amplifier;
current 2.37 muA;
pseudoresistor-less design;
size 0.18 mum;
voltage 1.8 V;
Capacitors;
Choppers (circuits);
DSL;
Electroencephalography;
Instruments;
Noise;
Switches;
73.
A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS
机译:
在40nm CMOS中的0.6V 6.4fJ /转换步长10位150MS / s细分SAR ADC
作者:
Yao-Sheng Hu
;
Chi-Huai Shih
;
Hung-Yen Tai
;
Hung-Wei Chen
;
Hsin-Shu Chen
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
analogue-digital conversion;
asynchronous circuits;
low-power electronics;
CMOS technology;
Nyquist rate;
conversion-step subranging SAR;
digital loop delay;
power 0.264 mW;
settling-time relief technique;
single-channel asynchronous subranging SAR ADC;
size 40 nm;
voltage 0.6 V;
word length 10 bit;
CMOS integrated circuits;
Capacitors;
Delays;
Noise;
Redundancy;
Switches;
Analog to digital converter (ADC);
settling time;
subranging;
successive approximation register (SAR);
74.
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process
机译:
具有65nm CMOS工艺的全数字时钟和数据恢复功能的26.5 Gb / s光接收器
作者:
Sang-Hyeok Chu
;
Woorham Bae
;
Gyu-Seob Jeong
;
Jiho Joo
;
Gyungock Kim
;
Deog-Kyoon Jeong
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
clock and data recovery circuits;
integrated optoelectronics;
jitter;
low-power electronics;
optical receivers;
CMOS process;
IEEE 802.3ba;
LA;
LC quadrature digitally controlled oscillator;
LC-QDCO;
TIA;
all-digital CDR;
all-digital clock and data recovery;
bit rate 25 Gbit/s;
bit rate 26.5 Gbit/s;
half-rate ADCDR;
inverter-based amplifier;
limiting amplifier;
low power consumption;
optical receiver;
power 254 mW;
quadrature sampling;
receiver sensitivity;
recovered clock jitter;
size 65 nm;
time 1.28 ps;
tolerance mask;
transimpedance amplifier;
CMOS integrated circuits;
Clocks;
Optical amplifiers;
Optical receivers;
Oscillators;
Semiconductor device measurement;
LC oscillator;
all-digital clock and data recovery (ADCDR);
optical;
quadrature digitally controlled oscillator (QDCO);
receiver;
transimpedance amplifier (TIA);
75.
A 103 pJ/bit multi-channel reconfigurable GMSK/PSK/16-QAM transmitter with band-shaping
机译:
具有频带整形功能的103 pJ / bit多通道可重配置GMSK / PSK / 16-QAM发送器
作者:
Xiayun Liu
;
Teng Kok Hin
;
Chun-Huat Heng
;
Yuan Gao
;
Wei-Da Toh
;
San-Jeow Cheng
;
Minkyu Je
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
frequency synthesizers;
minimum shift keying;
quadrature amplitude modulation;
radio transmitters;
band-shaping;
coupled DLL based phase interpolated synthesizer;
direct quadrature modulation;
injection-locked ring oscillator;
multichannel reconfigurable GMSK-PSK-16-QAM transmitter;
Calibration;
Energy efficiency;
Frequency shift keying;
Phase shift keying;
Transmitters;
band shaping;
energy efficiency;
injection locking;
reconfigurable;
transmitter;
76.
Mobile display technologies: Past, present and future
机译:
移动显示技术:过去,现在和未来
作者:
Ohshima Hiroyuki
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
colour displays;
liquid crystal displays;
smart phones;
thin film transistors;
touch sensitive screens;
user interfaces;
LCD;
TFT;
easy-to-use touch user interface;
form factor;
full color flat panel display;
future smart device;
liquid crystal display;
mobile display development;
mobile display market;
semiconductor technology;
smartphones;
tablet PC;
thin film transistor;
Glass;
Mobile communication;
Organic light emitting diodes;
Smart phones;
Substrates;
Thin film transistors;
TFT LCD;
mobile display;
smartphones;
77.
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
机译:
采用65nm CMOS技术的完全集成40Gb / s脉冲模式发生器和误码率测试仪芯片组
作者:
Guan-Sing Chen
;
Chin-Yang Wu
;
Chen-Lun Lin
;
Hao-Wei Hung
;
Jri Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
clock and data recovery circuits;
error statistics;
phase locked loops;
pulse generators;
test equipment;
CDR circuits;
CMOS technology;
PLL circuits;
bit error rate tester chipsets;
bit rate 40 Mbit/s to 40 Gbit/s;
external clock;
fully integrated pulse pattern generator;
size 65 nm;
ultrawide data range;
Bit error rate;
Boosting;
CMOS integrated circuits;
Clocks;
Gain;
Jitter;
Temperature sensors;
78.
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of −40 to 170°C with test screening against write disturb issues
机译:
适用于汽车MCU应用的40 nm双端口和两端口SRAM,适用于−40至170°C的宽温度范围,并具有针对写干扰问题的测试筛选
作者:
Yokoyama Yoshisato
;
Ishii Y.
;
Tanaka Kiyoshi
;
Fukuda Toshio
;
Tsujihashi Yoshiki
;
Miyanishi Astushi
;
Asayama Shinobu
;
Maekawa Keiichi
;
Shiba Kazutoshi
;
Nii Koji
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS memory circuits;
SRAM chips;
automotive electronics;
embedded systems;
failure analysis;
flash memories;
integrated circuit testing;
leakage currents;
microcontrollers;
1-read/1-write two-port SRAM;
2-read-write dual-port SRAM;
8T SRAM bitcell;
automotive MCU applications;
automotive microcontroller;
embedded flash CMOS technology;
leakage current reduction;
optimized process;
optimized sizing;
screening disturb failures;
size 40 nm;
temperature -40 degC to 170 degC;
test chips;
test circuits;
test screening;
two-port SRAMs;
voltage 0.7 V;
write disturb;
Automotive engineering;
CMOS integrated circuits;
Clocks;
Delays;
Layout;
Random access memory;
Tuning;
170°C;
40 nm;
6T;
8T;
ECU;
MCU;
SRAM;
disturb;
dual-port;
memory;
screening;
testability;
two-port;
79.
Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI
机译:
28nm UTBB FD-SOI中的超低压数据路径模块
作者:
Reyserhove Hans
;
Reynders Nele
;
Dehaene Wim
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
energy consumption;
integrated circuit design;
silicon-on-insulator;
UTBB FD-SOI technology;
energy 0.17 pJ;
energy consumption;
extensive back-gate biasing range;
frequency 35 MHz;
leakage reduction strategies;
minimum energy point;
multiply-accumulate datapath block;
size 28 nm;
speed/energy trade-off;
supply voltages;
ultra-low voltage datapath blocks;
voltage 0.5 V;
voltage 250 mV;
CMOS integrated circuits;
Energy consumption;
Energy measurement;
Logic gates;
MOS devices;
Transistors;
Voltage measurement;
80.
An 83 peak efficiency and 1.07W/mm2 power density Single Inductor 4-Output DC-DC converter with Bang-Bang Zeroth-Order Control
机译:
具有Bang-Bang零 sup>顺序控制的83%峰值效率和1.07W / mm 2 sup>功率密度单电感器4输出DC-DC转换器
作者:
Dongchul Park
;
Tae-Hwang Kong
;
Sukhwan Choi
;
Gyu-Hyeong Cho
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
DC-DC power convertors;
bang-bang control;
charge pump circuits;
comparators (circuits);
compensation;
filters;
phase detectors;
voltage control;
BBZOC;
BCD process;
SIMO buck converter;
bang-bang zeroth-order control;
charge pump;
comparator;
compensation design;
control scheme;
filter;
loop control;
phase detector;
power 1.04 W;
power 2.7 W;
power density;
single inductor multiple output buck converter;
single-inductor DC-DC converter;
size 0.35 mum;
voltage mode control;
Charge pumps;
Conferences;
DC-DC power converters;
Density measurement;
Inductors;
Switches;
Transient analysis;
Bang-Bang Control;
Comparator;
DC-DC Buck Converter;
Efficiency;
Filter;
Freewheeling;
PFD;
Power Density;
SIMO;
Single Inductor Multiple Output;
Zeroth-Order Control;
81.
Semiconductor innovation into the next decade
机译:
未来十年的半导体创新
作者:
Sun Jack Y.-C
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
monolithic integrated circuits;
semiconductor technology;
Internet of Things;
OIP platform;
TSMC;
big data analytics;
brain wave interfaces/communications;
cloud computing;
cognitive computing;
semiconductor innovation;
system scaling;
universal translators;
CMOS integrated circuits;
Ecosystems;
Energy efficiency;
Stacking;
Technological innovation;
Three-dimensional displays;
Transistors;
3DIC;
CMOS;
CoWoS;
InFO;
IoT;
Moore's Law;
ecosystem;
foundry;
platform;
sensor;
system scaling;
82.
RF transconductor linearization technique robust to process, voltage and temperature variations
机译:
射频跨导体线性化技术,可抵抗过程,电压和温度变化
作者:
Subramaniyan Harish Kundur
;
Klumperink Eric /A/. M.
;
Nauta Bram
;
Venkatesh Svetha
;
Kiaei Ali
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
linearisation techniques;
low noise amplifiers;
mixers (circuits);
radio receivers;
replica techniques;
software radio;
CMOS process;
IIP3 improvement;
RF transconductor linearization technique;
current domain mixer;
floating battery by-pass circuit;
inverter based LNTA design;
power consumption;
process variations;
reconfigurable linearized low noise transconductance amplifier design;
replica biasing;
resistive degeneration;
size 45 nm;
software-defined radio receiver;
temperature variations;
voltage variations;
CMOS integrated circuits;
Inverters;
Linearity;
MOSFET;
Noise;
Receivers;
Robustness;
CMOS;
Linearity;
PVT;
Receiver;
Software-defined Radio;
Transconductor;
Transconductor Figure-of-Merit;
robust circuit design;
83.
0.2 V 8T SRAM with improved bitline sensing using column-based data randomization
机译:
0.2 V 8T SRAM,具有基于列的数据随机化,具有改进的位线感测
作者:
Anh Tuan Do
;
Zhaochuan Lee
;
Bo Wang
;
Ik-Joon Chang
;
Kim Tony T.
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS logic circuits;
SRAM chips;
circuit feedback;
data analysis;
power consumption;
sensors;
shift registers;
8T SRAM;
CMOS technology;
LFSR;
access time;
accessed bit;
bitline boost biasing scheme;
bitline sensing margin improvement;
bitline swing degradation;
column-based data randomization;
data pattern;
memory size 16 KByte;
power 0.7 muW;
power consumption;
room temperate;
sensing window;
simplified linear feedback shift register;
size 65 nm;
subthreshold supply voltages;
test chips;
time 2.5 mus;
voltage 0.2 V;
Computer architecture;
Logic gates;
Low voltage;
Microprocessors;
Random access memory;
Sensors;
Solid state circuits;
84.
Highly improved SNR differential sensing method using parallel operation signaling for touch screen application
机译:
使用并行操作信令的高度改进的SNR差分传感方法,用于触摸屏应用
作者:
Sanghyun Heo
;
Hyunggun Ma
;
Jaejoon Kim
;
Bien Franklin
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
amplifiers;
band-pass filters;
calibration;
capacitive sensors;
continuous time filters;
delay circuits;
85.
CCM/GM relative skip energy control in single-inductor multiple-output DC-DC converter for wearable device power solution
机译:
用于可穿戴设备电源解决方案的单电感器多输出DC-DC转换器中的CCM / GM相对跳跃能量控制
作者:
Yi-Ping Su
;
Chiun-He Lin
;
Te-Fu Yang
;
Ru-Yu Huang
;
Wei-Chung Chen
;
Ke-Horng Chen
;
Ying-Hsi Lin
;
Tsung-Yen Tsai
;
Chao-Cheng Lee
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
DC-DC power convertors;
power control;
wearable computers;
CCM-GM relative skip energy control;
RSEC;
continuous conduction mode/green mode;
maximum output ripple;
relative skip energy control;
single-inductor multiple-output DC-DC converter;
voltage ripple;
wearable device power solution;
Biomedical monitoring;
DC-DC power converters;
Inductors;
Noise;
Switches;
Switching loss;
Voltage control;
absolute skip;
continuous conduction mode;
green mode;
relative skip energy control;
single-inductor multiple-output;
86.
An 87×49 mutual capacitance touch sensing IC enabling 0.5 mm-diameter stylus signal detection at 240 Hz-reporting-rate with palm rejection
机译:
87×49互电容触摸感应IC,能够以240 Hz的报告速率检测直径为0.5 mm的手写笔信号,并具有手掌抑制功能
作者:
Yoshida Shin-ichi
;
Hamaguchi Mutsumi
;
Morishita Takahiro
;
Shinjo Shintaro
;
Nagao Akira
;
Miyamoto Masayuki
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
digital signal processing chips;
filtering theory;
signal detection;
tactile sensors;
CMOS technology;
CVC;
SNR;
charge-to-voltage converter;
digital signal processor;
electrical noise;
frequency 240 Hz;
mutual capacitance touch sensing IC;
palm detection filter;
palm rejection;
palm signals;
power consumption;
sinusoidal noise;
size 0.5 mm;
stylus signal detection;
touch sensing system;
touch sensor sense channels;
Conferences;
Solid state circuits;
alternating drive;
mutual capacitance;
palm rejection;
stylus;
touch sensing;
87.
Wide-supply-range all-digital leakage variation sensor for on-chip process and temperature monitoring
机译:
范围广泛的全数字泄漏变化传感器,用于片上过程和温度监控
作者:
Mahfuzul Islam A.K.M.
;
Shiomi Jun
;
Ishihara Takuya
;
Onodera Hidetoshi
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
MOSFET;
estimation theory;
large scale integration;
leakage currents;
LSI;
all-digital on-chip circuit;
all-digital-leakage variation sensor;
cell-base design approach;
leakage current variations;
nMOSFET;
pMOSFET;
reconfigurable inhomogeneity;
single monitor instance;
statistical properties;
temperature monitoring;
threshold voltage variation;
Delays;
Inverters;
Leakage currents;
MOSFET circuits;
Monitoring;
Temperature measurement;
Temperature sensors;
88.
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor
机译:
间歇驱动的电源电流均衡器,可在耐CPA的128位AES加密处理器中节省11倍和4倍的功耗
作者:
Miura Naruhisa
;
Fujimoto Daisuke
;
Korenaga Rie
;
Matsuda Keisuke
;
Nagata M.
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS logic circuits;
comparators (circuits);
cryptography;
equalisers;
low-power electronics;
CMOS integrated circuit;
CPA resistant AES cryptographic processor;
correlation power analysis attack;
equalizer power overhead;
intermittent driven supply current equalizer;
intermittent equalizer;
level shift comparator;
low power intermittent operation;
minimum hardware overhead;
power overhead savings;
processing rounds;
secret key protection;
size 0.18 mum;
test chip measurement;
thru operation mode;
CMOS integrated circuits;
Ciphers;
Correlation;
Equalizers;
Power demand;
Semiconductor device measurement;
89.
54 GHz CMOS LNAs with 3.6 dB NF and 28.2 dB gain using transformer feedback Gm-boosting technique
机译:
采用变压器反馈Gm增强技术的具有3.6 dB NF和28.2 dB增益的54 GHz CMOS LNA
作者:
Shita Guo
;
Tianzuo Xi
;
Ping Gui
;
Jing Zhang
;
Wooyeol Choi
;
Kenneth K.O.
;
Yanli Fan
;
Daquan Huang
;
Gu R.
;
Morgan Mark
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
low noise amplifiers;
millimetre wave amplifiers;
millimetre wave integrated circuits;
V-band CMOS LNA;
current 18 mA;
frequency 53.5 GHz;
frequency 53.9 GHz;
frequency 54 GHz;
frequency 54.2 GHz;
gain 25.4 dB;
gain 28.2 dB;
gain 3.8 dB;
low-noise amplifier;
noise figure;
noise figure 3.6 dB;
noise reduction;
size 65 nm;
transformer feedback Gm-boosting;
transmission-line;
voltage 1.1 V;
CMOS integrated circuits;
Gain;
Noise;
Noise figure;
Topology;
Transistors;
Low-noise amplifier (LNA);
V-band;
noise figure (NF);
power gain;
transformer;
transmission-line;
90.
An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS
机译:
采用0.18μmSOI CMOS的超低成本ESD保护的0.65dB NF + 10dBm OP1dB GNSS LNA
作者:
Fei Song
;
Tan Sam Chun-Geik
;
Shanaa Osama
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS analogue integrated circuits;
circuit stability;
electrostatic discharge;
integrated circuit packaging;
lead bonding;
low noise amplifiers;
satellite navigation;
silicon-on-insulator;
transistor circuits;
6-pin LGA package;
CDM ESD tests;
HBM;
SOI CMOS process;
bond wire;
class-AB mode;
current 5.9 mA;
external series inductor;
gain 19.2 dB;
input common-source transistor;
input matching;
noise figure 0.65 dB;
quiescent current;
size 0.18 mum;
source-degeneration;
ultra-low NF;
ultra-low-cost ESD-protected GNSS LNA;
voltage 2.5 kV;
voltage 2.8 V;
voltage 200 V;
voltage 250 V;
weak inversion region;
CMOS integrated circuits;
Electrostatic discharges;
Field effect transistors;
Global Positioning System;
Inductors;
Linearity;
Noise measurement;
91.
CMOS THz transmissive imaging system
机译:
CMOS THz透射成像系统
作者:
Tzu-Chao Yan
;
Chun-Hsing Li
;
Chih-Wei Lai
;
Wei-Cheng Chen
;
Tzu-Yuan Chao
;
Chien-Nan Kuo
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS image sensors;
MMIC oscillators;
antenna arrays;
submillimetre wave oscillators;
system-on-package;
terahertz wave imaging;
BCB carrier;
Benzocyclobutene carrier;
CMOS THz transmissive imaging system;
CMOS technology;
SoP technique;
antenna array;
frequency 332 GHz;
frequency 338 GHz;
measured EIRP;
measured maximum responsivity;
oscillator;
power 37.5 mW;
power 7.92 mW;
signal sensor;
signal source;
size 0.18 mum;
size 40 nm;
system-on-package technique;
Antenna arrays;
CMOS integrated circuits;
CMOS technology;
Detectors;
Imaging;
Lenses;
Solid state circuits;
CMOS;
System-on-Package (SoP);
THz imaging system;
signal sensor;
signal source;
92.
23Gbps 9.4pJ/bit 80/100GHz band CMOS transceiver with on-board antenna for short-range communication
机译:
具有板载天线的23Gbps 9.4pJ / bit 80 / 100GHz波段CMOS收发器,用于短距离通信
作者:
Nakajima Kensuke
;
Maruyama Akihiro
;
Kohtani Masato
;
Sugiura Toshihiko
;
Otobe Eiichiro
;
Jaejin Lee
;
Shinhee Cho
;
Kyusub Kwak
;
Jeongseok Lee
;
Yoshimasu Toshihiko
;
Fujishima Minoru
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
amplitude shift keying;
field effect MIMIC;
millimetre wave antennas;
power consumption;
radio transceivers;
ASK method;
CMOS transceiver;
IEEE802.11ad;
W-band;
bit rate 23 Gbit/s;
frequency 60 GHz to 110 GHz;
fully integrated transceiver ICs;
high-speed-short-range wireless communication system;
noncoherent amplitude shift keying modulation method;
on-board antenna;
power 216 mW;
power consumption;
short-range communication;
size 65 nm;
transceiver architecture;
Amplitude shift keying;
Antenna measurements;
Antennas;
CMOS integrated circuits;
Power demand;
Transceivers;
Wireless communication;
CMOS;
antenna;
data rate;
millimeter-wave;
transceiver;
93.
0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS
机译:
40nm LP CMOS中的0.339fJ /位/搜索节能TCAM宏设计
作者:
Po-Tsang Huang
;
Shu-Lin Lai
;
Ching-Te Chuang
;
Wei Hwang
;
Huang Jie
;
Hu Anping
;
Kan Paul
;
Jia Mingming
;
Lv Kimi
;
Zhang Boming
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS memory circuits;
energy conservation;
integrated circuit design;
low-power electronics;
power control;
LP CMOS;
LP process;
TCAM cell;
TCAM macrodesign;
column-based data-aware power control;
don't-care-based ripple bit-lines;
don't-care-based ripple search-lines;
energy efficiency;
gate oxide;
leakage power reduction;
low power CMOS;
p-type comparison circuits;
search-line power reduction;
size 40 nm;
ternary content addressable memory;
wire capacitance;
write-ability improvements;
CMOS integrated circuits;
CMOS process;
Capacitance;
Delays;
Energy efficiency;
Logic gates;
Switches;
Embedded memory;
TCAM;
energy-efficient;
94.
Energy efficient computing in nanoscale CMOS: Challenges and opportunities
机译:
纳米级CMOS中的节能计算:挑战与机遇
作者:
De Vivek
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS digital integrated circuits;
integrated circuit design;
integrated circuit reliability;
system-on-chip;
SoC designs;
activity changes;
aging-induced degradations;
device parameter variations;
energy efficient computing;
exascale supercomputers;
excursions;
magnitude improvements;
nanoscale CMOS;
nanoscale CMOS process;
reliability considerations;
supply noises;
system-on-chip designs;
temperature;
voltage-frequency operating range;
wearable devices;
workload;
CMOS integrated circuits;
Energy efficiency;
Noise;
Robustness;
System-on-chip;
Temperature sensors;
Voltage control;
CMOS;
NTV;
SoC;
energy efficiency;
power management;
variations;
95.
An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64 in 16nm FinFET
机译:
超紧凑,未修剪的CMOS带隙基准,在16nm FinFET中3σ误差为+ 0.64%
作者:
Chin-Ho Chang
;
Jaw-Juinn Horng
;
Kundu A.
;
Chih-Chiang Chang
;
Yung-Chow Peng
会议名称:
《IEEE Asian Solid State Circuits Conference》
|
2014年
关键词:
CMOS integrated circuits;
MOSFET;
energy gap;
integrated circuit layout;
reference circuits;
TC performance;
TSMC FinFET process;
chip area reduction;
high-accuracy applications;
layout floorplan;
medium accuracy applications;
size 16 nm;
stage stack-gate;
temperature 40 degC to 125 degC;
ultracompact untrimmed CMOS bandgap reference circuit;
voltage 1 V;
Arrays;
Layout;
Logic gates;
Mirrors;
Photonic band gap;
Temperature measurement;
Transistors;
Bandgap voltage reference;
FinFET circuit;
MOS array layout;
current mirror;
opamp;
stack gate;
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