CMOS analogue integrated circuits; clock and data recovery circuits; decision feedback equalisers; interference suppression; intersymbol interference; jitter; receivers; relaxation oscillators; 2 tap-DFE embedded clock and data recovery circuit; CMOS technology; CTLE; ISI; Nyquist frequency; bit rate 19 Gbit/s to 27 Gbit/s; broadband PLL; channel loss compensation; continuous time linear equalizer; decision feedback equalizer; high energy efficiency; hybrid CDR; jitter suppression; loss 20 dB; quadrature relaxation type oscillator; receiver; sampling phases; size 40 nm; Clocks; Decision feedback equalizers; Engines; Jitter; Least squares approximations; Phase locked loops; Receivers; CDR; CTLE; DFE; PLL;
机译:一个3.12 pJ /位,19-27 Gbps接收器,带有2抽头DFE嵌入式时钟和数据恢复
机译:具有波特率时钟和数据恢复功能的25Gb / s,2.1pJ / bit,全集成光接收机
机译:24位/秒独立于输入数据的时钟和数据恢复,利用位有效的编织时钟信号和固定的嵌入式过渡实现8K-UHD面板内接口
机译:3.12 PJ /位,19-27 Gbps接收器,具有2个点击DFE嵌入式时钟和数据恢复
机译:适用于0.18um CMOS的10 Gbps宽带接收器的时钟和数据恢复电路。
机译:病毒检测呈阳性的27例出院COVID-19患者的肺炎恢复
机译:利用深亚微米数字CmOs技术设计和实现2.4 Gbps - 3.2 Gbps时钟和数据恢复电路