Clock and data recovery circuits for 10 giga-bit-per-second broadband receivers in 0.18mum CMOS.

摘要

Clock and data recovery (CDR) circuit is the most important and essential part of any broadband receiver. Such receivers serve in many applications, including optical communications, backplane routing, and chip-to-chip interconnects. CDR circuits extract a clock from the asynchronous and noisy received data and retime the data such that the jitter accumulated during transmission is removed.; High-speed CDR design must deal with many circuit and architecture issues, including jitter, skews, and acquisition of lock. CDR circuits must satisfy stringent specifications defined by communication standards, especially for the jitter specification and the frequency locking range.; This thesis focuses on the design of high-speed CMOS CDR circuits for broadband communication. An emphasis is placed on the design of phase detectors. The specific research contributions of this work include (1) design and analysis of high speed CDR architectures and circuits, (2) introduction of a novel phase detector with ajustable Kpd. With the novel phase detector, the single-loop CDR circuit can have both excellent jitter performance and wide frequency locking range, which is extremely difficult to achieve using conventional phase detectors. As a demonstration, a 10Gb/s CMOS CDR with the proposed phase detector was designed and fabricated. The chip measurement results are also presented.