CMOS integrated circuits; DRAM chips; equalisers; system-in-package; transceivers; CMOS; DRAM interface; SiP; bit rate 16.8 Gbit/s; continuous time linear equalizer; feed forward equalizer; multiplexer; silicon carrier channel; single ended signaling; single ended transceiver; size 65 nm; source follower; Bit error rate; CMOS integrated circuits; Random access memory; Receivers; Sensors; Silicon; Transceivers; BER and 120Ω terminations; CTLE; FFE; Self Vref Generator; SiP based DRAM Interface; Single Ended Transceiver;
机译:用于Si载波通道上基于SiP的DRAM接口的65 nm CMOS中的16.8 Gbps /通道单端收发器
机译:用于点对点DRAM接口的具有四位四线四电平平衡编码的单端并行收发器
机译:具有TIA RX端接的80 mV摆动单端双二进制收发器,用于点对点DRAM接口
机译:SI载波通道上的SIP基于SIP的SIP DRAM接口65nm CMOS中的16.8Gbps /通道单端收发器
机译:用于基于DSP的PRML磁盘读取通道的高速CMOS模数接口实现的电路技术和注意事项。
机译:用于基于SiPM的正电子发射断层成像系统的CMOS前端接口ASIC
机译:一个4通道的多标准自适应串行收发器,范围为1.25-10.3GB / s,CMOS 65nm