Circuit techniques and considerations for implementation of high speed CMOS analog-to-digital interfaces for DSP-based PRML magnetic disk read channels.

摘要

In order to meet the demands of ever increasing storage capacity and transfer rate requirements in magnetic storage devices, sophisticated signal processing methods are being applied to the magnetic disk drive channel. One approach in particular, Class IV Partial Response with Maximum Likelihood detection (Class IV PRML) appears to be gaining widespread acceptance in the industry as the first of possibly many discrete-time detection approaches that will be used in commercial drives to meet this end. In systems employing Class IV PRML signalling, the read channel electronics resembles a baseband communication receiver requiring functions such as symbol-rate timing recovery, adaptive equalization, and sequence detection. These functions are often performed in the digital domain which facilitates implementation of robust digital equalizers with 6 or more taps. A key element required in these DSP-based channels is the analog-to-digital interface which performs lowpass filtering, possibly some signal pre-conditioning in the form of coarse equalization, sampling, and the analog-to-digital conversion. Due to the off-disk signal-to-noise ratio, the resolution requirements of the A/D converter are on the order of 5-6 bits.;Economical implementation of the analog-to-digital interface in terms of both power and cost is a key problem with implementation of Class IV PRML channels. In particular, implementation of the lowpass filter and pre-equalizer are key problems using conventional techniques requiring the use of either BiCMOS technology or external components.;This thesis describes circuit techniques that can be used to provide the analog-to-digital interface function in CMOS at speeds higher than otherwise possible using conventional approaches. A new switched-capacitor filter architecture is described which employs parallel structures allowing amplifiers multiple output periods for settling and thus breaking the speed bottleneck of conventional switched-capacitor filters. Both single- and multi-rate filters can be implemented allowing the implementation of high sampling rate decimation filters which may be used in the front-end lowpass filter when preceded by a non-critical continuous-time filter which provides attenuation near the sampling rate. A prototype integrated-circuit was designed and built in order to demonstrate the circuit techniques developed in this research. The prototype IC contains a lowpass filter, programmable equalizer, 6-bit analog-to-digital converter, and required clock generation and operates with a sampling rate of 100 MHz with 6 bits of resolution in a conservative 1.2 ;There are two main parts to this thesis. The first part is a presentation of fundamentals of both digital communication theory and of how data is retrieved in the magnetic disk channel. This provides a background upon which the block level architecture of the prototype can be justified. In particular, we examine the motivation from a system level for equalization prior to the analog-to-digital converter in a system with a digital adaptive equalizer. The second part is a description of the new circuit techniques and architectures developed to achieve higher operating frequencies than possible using conventional approaches. This thesis demonstrates the feasibility of parallel structures in analog processing to achieve both high speed filtering and data conversion and the advantages of analog equalization in DSP-based communication receivers.