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An ultra-compact, untrimmed CMOS bandgap reference with 3σ inaccuracy of +0.64 in 16nm FinFET

机译:超紧凑,未修剪的CMOS带隙基准,在16nm FinFET中3σ误差为+ 0.64%

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An ultra-compact sub-1V CMOS bandgap reference circuit is presented. To reduce the chip area the proposed bandgap is realized with 40 stage stack-gate, which adopts a novel layout floorplan without any area penalty. This paper describes two bandgap circuits and are both fabricated in TSMC 16nm FinFET process. The first bandgap aims at applications requiring small-area (area 0.0023 mm) that achieves medium accuracy (3σ 1.67%) without trimming. The second bandgap aims at high-accuracy applications (area 0.013 mm) that achieve 3σ 0.64% without trimming. Both bandgap circuits have good TC performance less than 35ppm/°C between -40°C to 125°C. We claim to have the smallest chip area and highest accuracy when compared to the present state-of-the-art untrimmed CMOS bandgap circuits.
机译:提出了一种超紧凑的低于1V的CMOS带隙基准电路。为了减少芯片面积,建议的带隙采用40级堆叠门实现,采用了新颖的布局布局,没有任何面积损失。本文介绍了两个带隙电路,它们均采用台积电16nm FinFET工艺制造。第一个带隙针对需要小面积(0.0023毫米)的区域而无需修整即可达到中等精度(3σ1.67%)的应用。第二个带隙适用于高精度应用(面积0.013 mm),无需修整即可达到3σ0.64%。两个带隙电路在-40°C至125°C之间的TC性能均低于35ppm /°C。与目前最先进的未修整CMOS带隙电路相比,我们声称具有最小的芯片面积和最高的精度。

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