CMOS digital integrated circuits; clocks; delay lock loops; integrated circuit design; low-power electronics; power consumption; CMOS; all-digital delay-locked loop; automatic bypassing; clock frequency; clock gating; closed-loop ADDLL; coarse locking; cyclic delay deduction; cyclic half-delay-line architecture; frequency 3 MHz to 1.8 GHz; power 94 muW to 9.5 mW; power consumption; size 0.0153 mm; size 65 nm; CMOS integrated circuits; Clocks; Delay lines; Delays; Jitter; Power demand; Radiation detectors; ADDLL; low power; small area; wide range;
机译:采用65nm CMOS技术的600kHz至1.2GHz全数字延迟锁定环路
机译:采用0.13 $ mu {hbox {m}} $ CMOS技术的2.5 GHz全数字延迟锁定环
机译:在65纳米CMOS工艺中基于延迟锁定环路的时钟和数据恢复具有宽工作范围和低抖动
机译:3 MHz至-1.8 GHz94μW至-9.5 MW 0.0153-mm 2 sup>在65-nm cmos中的全数字延时锁定环
机译:低抖动,宽锁定范围全数字锁相环和延迟锁相环的研究和设计。
机译:具有可调范围CMOS延迟锁定环路的亚皮秒抖动设计适用于高速和低功耗应用
机译:用于蓝牙LE的0.5V 1.6-MW 2.4-GHz Fractional-N全数字PLL,采用PVT - 不敏感TDC,使用28-NM CMOS中的开关电容倍增器