All-digital multiplying delay-locked loop with a delta-sigma dithering cell

摘要

Phase error between the present invention delta-sigma dither cell-based all-digital as multiplying the delay of the locked loop circuit, the input clock signal (clk ref) input receives an input clock signal (clk ref) and the output clock signal (clk out) a digitally controlled multiplexed ring oscillator that reduces the frequency of the output clock signal to within a preset delay resolution and at the same time multiplies the frequency of the output clock signal by N times that of the input clock signal; a decoder for generating a control signal for controlling the operation of the digitally controlled multiplexed ring oscillator; a delta sigma modulator for generating a control signal of the decoder to control a dithering cell of the multiplexed ring oscillator; and a digital loop filter receiving the input clock signal clk ref and generating a digital loop filter output signal for controlling the decoder and the delta sigma modulator. is provided