A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration

摘要

A 12 bit CMOS current-steering digital-to-analog converter (DAC) in 0.11 μm CMOS technology is presented for IQ baseband wireless transmitter and envelop tracking (ET) power amplifier that requires low power consumption with flexible swing and common-mode controls. The conventional half clock period return-to-zero (RZ) effectively eliminates code-dependent transient but results in amplitude loss. The proposed controllable RZ window less than 50 % of clock duty cycle mitigates such signal loss, and yet achieves the spurious-free dynamic range (SFDR) better than 70 dB up to Nyquist bandwidth at the sample frequency of 250 MHz. The core area of DAC is 0.117 mm and it dissipates about 28 mW under 2.5 V supply.