机译:一个12位250 MS / s 28 mW + 70 dB SFDR非50%RZ DAC,采用0.11μmCMOS,使用可控制的RZ窗口进行无线SoC集成
Gwangju Inst Sci & Technol, Sch Elect Engn & Comp Sci, Bukgu, South Korea;
Silicon Works, Business Div, Driver IC Team, Daejeon, South Korea;
Gwangju Inst Sci & Technol, Sch Elect Engn & Comp Sci, Bukgu, South Korea;
Digital-to-analog converter (DAC); Dynamic-element matching (DEM); Return-to-zero (RZ); Spurious-free dynamic range (SFDR); Signal-to-noise ratio (SNR); Noise spectral density (NSD);
机译:具有0.13μmCMOS的78位SFDR的12位250 MS / s流水线ADC
机译:具有0.6- / splμ/ m CMOS的3.3V 12-b 50-MS / s A / D转换器,具有超过80dB的SFDR
机译:具有DfT时钟且存储器达到SFDR> 50 dB且高达1 GHz的28nm CMOS 7-GS / s 6位DAC
机译:使用可控制的RZ窗口,0.11μmCMOS的12位250 MS / s 28 mW +70 dB SFDR DAC,用于无线SoC集成