CMOS integrated circuits; FIR filters; UHF filters; array signal processing; circuit feedback; clocks; compensation; continuous time filters; delays; digital control; digital-analogue conversion; jitter; matrix algebra; modulators; sensitivity analysis; 3-tap FIR feedback DAC; 3rd-order continuous-time modulator; BW; CMOS process; SNDR continuous-time modulator; bandwidth 15 MHz; clock jitter; core modulator; digital ELD compensation; digitally controlled reference switching matrix; error signal reduction; frequency 1.2 GHz; highly-digital excess loop delay compensation; loop filter linearity enhancement; lower sensitivity; multibit FIR feedback; power-hungry adder; signal bandwidth; size 65 nm; ultrasound beamformer; voltage 1 V; Clocks; Delays; Finite impulse response filters; Jitter; Modulation; Resistors; Switches;
机译:具有2.2 MHz带宽和90.4 dB SNDR的4.5 mW CT自耦合
机译:使用低噪声高线性反馈DAC的6mW,70.1dB SNDR和20MHz BW连续时间Sigma-Delta调制器
机译:具有异步顺序量化器和数字过大环路延迟补偿的0.89mW 1MHz 62dB SNDR连续时间Delta-Sigma调制器
机译:A 1 V 59 FJ / STEP 15 MHz BW 74 DB SNDR连续时间ΔΣ调制器,具有数字ELD补偿和多点FIR反馈
机译:一个0.2至2MHz带宽,50至86dB SNDR,16至22mW灵活的四阶ΣΔ调制器,在1.2V 90nm CMOS中具有DC至44MHz可调中心频率