CMOS integrated circuits; low-power electronics; phase locked loops; radio transceivers; CMOS technology; PCIE; PLL; QSGMII; RXAUI; SATA; SGMII; USB3; XAUI; bit rate 1.2 Gbit/s to 6.8 Gbit/s; circuit technique; communication standards; low-power multistandard transceiver design; power 23 mW; power consumption; single-lane transceiver; voltage 0.9 V; CMOS integrated circuits; Clocks; Jitter; Phase locked loops; Receivers; Standards; Transceivers; clock and data recovery; high speed integrated circuits; serializer-deserializers; transceivers;
机译:使用130nm CMOS技术进行多标准应用的集成多频段RF收发器设计
机译:用于0.18μmCMOS工艺中制造的多标准无线收发器的分数N分频器
机译:用于多标准光纤通信系统的CMOS字对齐可配置收发器
机译:23MW / LANE 1.2-6.8GB / S在28nm CMOS中的多标准收发器
机译:用于多标准无线通信的CMOS射频功率放大器。
机译:低功耗CmOs BFsK收发器用于健康监测系统
机译:一个4通道的多标准自适应串行收发器,范围为1.25-10.3 GB / s,CMOS 65 nm