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A 0.1–1.5GHz harmonic rejection receiver front-end with hybrid 8 phase LO generator, phase ambiguity correction and vector gain calibration

机译:一个0.1–1.5GHz谐波抑制接收器前端,具有混合8相LO发生器,相位歧义校正和矢量增益校准

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A 0.1-1.5GHz harmonic rejection (HR) receiver front-end is presented. A flexible HR mixer is proposed to correct phase ambiguity, and a vector gain calibration is used to eliminate the gain/phase mismatch and improve the HR ratio. With the proposed hybrid 8 phase local oscillating (LO) generator, the highest carrier frequency from the frequency synthesizer is only twice of the desired LO frequency. The HR receiver has been implemented in 65nm CMOS. With 1.8mm core chip area and 5.4-24.5mA current consumption from a 1.2V power supply, the receiver achieves 85dB conversion gain, 4.3dB NF, +13dBm/+14dBm IB/OB-IIP3, >54/56 dB HR3/HR5 with 30-40dB improvement by calibration, and 2.3% EVM with 32QAM modulation signal.
机译:提出了一个0.1-1.5GHz谐波抑制(HR)接收机前端。提出了一种灵活的HR混频器来校正相位模糊度,并使用矢量增益校准来消除增益/相位不匹配并提高HR比。使用建议的混合8相本地振荡(LO)发生器,频率合成器的最高载波频率仅为所需LO频率的两倍。 HR接收器已在65nm CMOS中实现。接收器采用1.2V电源时具有1.8mm的核心芯片面积和5.4-24.5mA的电流消耗,接收器可实现85dB的转换增益,4.3dB的NF,+ 13dBm / + 14dBm的IB / OB-IIP3,> 54/56 dB的HR3 / HR5通过校准可将性能提高30-40dB,并具有32QAM调制信号的2.3%EVM。

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