首页> 外文期刊>IEEE transactions on very large scale integration (VLSI) systems >A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration
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A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

机译:0.9-5.8 GHz软件定义的接收器射频前端,具有基于变压器的电流增益增强和谐波抑制校准

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A 0.9-5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between -1.6 and -12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66-82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm.
机译:一个0.9-5.8 GHz接收器RF前端(RFE),集成了双频带低噪声跨导放大器(LNTA),无源谐波抑制(HR)下变频混频器和用于软件的全数字频率合成器定义了无线电。用作LNTA和混频器之间接口的可切换三线圈变压器除了具有宽带操作能力外,还具有电流增益提升功能。为混频器实现了自动本地振荡器相位误差检测和校准电路,以实现高HR比(HRR)。 RFE采用65 nm CMOS制成,测量的噪声系数在2.9至3.8 dB之间,三阶输入截取点(IIP3)在-1.6至-12.8 dBm之间,三阶HRR为81 dB,五阶HRR为70 dB,而1.2V电源消耗66-82 mA的电流,占用4.2 mm的芯片面积。

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