Simultaneous power supply, threshold voltage, and transistor sizeoptimization for low-power operation of CMOS circuits

摘要

This paper demonstrates a new approach for minimizing the total ofnthe static and the dynamic power dissipation components in ancomplementary metal-oxide-semiconductor (CMOS) logic network required tonoperate at a specified clock frequency. The algorithms presented can benused to design ultralow-power CMOS logic circuits by joint optimizationnof supply voltage, threshold voltage and device widths. The static,ndynamic and short-circuit energy components are considered and annefficient heuristic is developed that delivers over an order ofnmagnitude savings in power over conventional optimization methods