摘要：随着工艺特征尺寸的缩进,为了进一步提高数据处理速度,多核片上系统(MPSoC)成为一种必然的选择.片上网络(NoC)作为多核片上系统的通信部分,其设计影响了整个系统的性能.本文研究了 2种不同的片上网络设计,探讨了路由器结构的改变对 MPSoC性能的影响.对于采用低延迟优化设计的路由器,通过 ModelSim仿真得到数据帧的最优传输延迟减少了 6倍.同时,分别完成了该MPSoC的FPGA和ASIC实现,基于实现结果定量分析了在0.13 μm工艺尺寸下2种实现方式的面积和延时差距.结果表明,FPGA实现与 ASIC实现的面积比率大约为 29~33:1,延时比率大约为 4.5~7.5:1.%With the scaling of Complementary Metal Oxide Semiconductor(CMOS) process, Multi-Processor System-on-Chip(MPSoC) is becoming a preferable way to improve the rate of data processing. Because Network-on-Chip(NoC) is the key part of MPSoC,acting as the communication medium, the design of NoC would influence the performance of the whole system. Two different NoCs are studied and the influence of router structure on MPSoC is discussed. Experimental results obtained through ModelSim simulation show that the transmission latency of the router with delay optimization techniques has decreased by 6 times. Besides,the MPSoC on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits(ASIC) are implemented respectively. The areas and critical delay gap between them through two corresponding synthesis Computer Aided Design(CAD) flows in 0.13μm process are measured. The area of FPGA is roughly 29 to 33 times that of ASIC, and the critical delay of FPGA is 4.5 to 7.5 times that of ASIC.
