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首页> 外文期刊>Microelectronics & Reliability >Test structure assembly for bump bond yield measurement on high density flip chip technologies
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Test structure assembly for bump bond yield measurement on high density flip chip technologies

机译:用于在高密度倒装芯片技术上测量凸点键合良率的测试结构组件

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摘要

Modern flip chip technologies for imaging applications have achieved a very high integration level together with the possibility of large area assemblies. These developments have resulted in an enormous increase in the total number of bump bonds per assembly. Consequently, yield tests become difficult, and an accurate measurement of it is often discarded. This problem is aggravated in medical applications, where the critical information can be limited to a few pixels, and therefore, yield should be very close to 100%. In these cases, a variation of a small percentage in bump bond yield can make the difference between an usable and a non-usable assembly. Therefore, quantitative and precise measurement of bump bond yield is needed to characterize the quality of any high density flip chip technology for these applications. In this paper, we present a newly developed test structure for electrical measurement of the bump bond yield of high density flip chip technologies, allowing both optimization and statistical control of the process. This test structure facilitates the identification of possible process deviations with precise quantitative yield measurements. It also allows to pin point any localized systematic failure in the bump bonding process. The test structure has been used to evaluate the yield of different flip chip technologies and has contributed to their fine optimization where necessary.
机译:用于成像应用的现代倒装芯片技术已经实现了很高的集成度,并且具有大面积组装的可能性。这些发展导致每个组件的凸点结合总数大大增加。因此,良率测试变得困难,并且常常不对其进行准确的测量。在关键信息可以限制在几个像素的医疗应用中,这个问题会更加严重,因此良率应该非常接近100%。在这些情况下,凸点键合良率的小百分比变化会导致可用组件和不可用组件之间的差异。因此,需要对凸点焊合格率进行定量和精确的测量,以表征用于这些应用的任何高密度倒装芯片技术的质量。在本文中,我们提出了一种新开发的测试结构,用于对高密度倒装芯片技术的凸点键合良率进行电测量,从而可以对过程进行优化和统计控制。这种测试结构有助于通过精确的定量产量测量来确定可能的工艺偏差。它还允许在凸点键合过程中查明任何局部的系统故障。该测试结构已用于评估不同倒装芯片技术的成品率,并在必要时有助于其精细优化。

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