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IEEE International Conference on Microelectronic Test Structures
IEEE International Conference on Microelectronic Test Structures
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1.
New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors
机译:
CMOS晶体管栅极电压相关串联电阻提取的新方法
作者:
Brut H.
;
Juge A.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
1997年
2.
Test structure for mismatch characterization of MOS transistors in subthreshold regime
机译:
亚阈值制度中MOS晶体管不匹配表征的测试结构
作者:
Conti M.
;
Dalla Betta G.F.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
1997年
3.
Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions
机译:
数字测试电路设计与优化AC热载波可靠性表征和逼真高频应力条件下的型号校准
作者:
Jiang W.
;
Le H.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
1997年
4.
Electrical linewidth test structures fabricated in mono-crystalline films for reference-material applications
机译:
电气线宽测试结构,用于参考材料的单晶膜中制造
作者:
Cresswell M.W.
;
Sniegowski J.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
1997年
5.
A Test Structure To Measure The misalignment between Poly-si And Diffusion layers
机译:
测量多Si和扩散层之间未对准的测试结构
作者:
Mi Jian
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
6.
Automatic test structure modification
机译:
自动测试结构修改
作者:
Golshan K.
;
Shetti S.S.M.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
7.
Statistical Significance Of Defect density Estimates
机译:
缺陷密度估计的统计显着性
作者:
Kaempf U.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
8.
Comparison Of Results From Simple Expressions For MOSFET Parameter Extraction
机译:
用于MOSFET参数提取的简单表达结果的比较
作者:
Buemer M.G.
;
Lin Y-S.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
9.
The Design And Calibration Of A Semiconductor Strain Gauge Array
机译:
半导体应变仪阵列的设计与校准
作者:
S.A. Gee
;
Akylas V.R.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
10.
A new method for precise evaluation of dynamic recovery of negative bias temperature instability
机译:
一种新方法,精确评估负偏置温度不稳定的动态恢复
作者:
Aota S.
;
Fujii S.
;
Jin Z.W.
;
Ito Y.
;
Utsumi K.
;
Morifuji E.
;
Yamada S.
;
Matsuoka F.
;
Noguchi T.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
thermal stability;
electric current;
MOSFET;
parameter estimation;
electric potential;
MOS integrated circuits;
negative bias temperature instability;
dynamic recovery;
drain current;
degradation estimation;
gate stress;
measurement system;
large-scale-integrated devices;
11.
90nm CMOS technology characterization at transfer and ramp
机译:
90nm CMOS技术表征转移和坡道
作者:
Kelleher A.
;
Gourley D.
;
Holmes A.M.
;
Hepburn T.
;
Farrell C.
;
Groves R.
;
Taskin T.
;
McMillan J.
;
Rawlins W.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
nanoelectronics;
CMOS integrated circuits;
integrated circuit measurement;
integrated circuit yield;
high yielding technology;
CMOS technology transfer;
CMOS technology ramp;
matching requirements;
characterization requirements;
90 nm;
300 mm;
12.
Excess Base Current Model for Gamma-Irradiated SiGe Bipolar Transistors
机译:
用于伽马照射SiGe双极晶体管的过量基础电流模型
作者:
Ullan M.
;
Alegre J. P.
;
Diez S.
;
Pellegrini G.
;
Campabadal F.
;
Lozano M.
;
Lora-Tamayo E.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
关键词:
Gamma radiation;
SiGe;
SiGe HBT;
bipolar transistors;
hardness assurance;
ionization damage;
radiation effects;
reliability modeling;
semiconductor device modeling;
13.
A New Test Structure for Shallow Trench Isolation (STI) Depth Monitor
机译:
浅沟槽隔离(STI)深度监视器的新测试结构
作者:
Wang Qingfeng
;
Pendharkar Sameer
;
Hu Binghua
;
Russell Bill
;
Jones-Williams Pam
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
关键词:
Depth;
Etest;
Monitor;
P-body;
Pinch Resistor;
Shallow Trench Isolation (STI);
14.
Excess Base Current Model for Gamma-Irradiated SiGe Bipolar Transistors
机译:
用于伽马照射SiGe双极晶体管的过量基础电流模型
作者:
M. Ullan
;
J. P. Alegre
;
S. Diez
;
G. Pellegrini
;
F. Campabadal
;
M. Lozano
;
E. Lora-Tamayo
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
关键词:
Gamma radiation;
Radiation effects;
Ionization damage;
Hardness assurance;
Bipolar transistors;
SiGe;
SiGe HBT;
Reliability modeling;
Semiconductor device modeling;
15.
Novel parameter extraction method for low field drain current of nano-scaled MOSFETs
机译:
纳米MOSFET低场漏电流的新型参数提取方法
作者:
Tanaka Takuji
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
16.
A New Test Structure for Shallow Trench Isolation (STI) Depth Monitor
机译:
浅沟槽隔离(STI)深度监视器的新测试结构
作者:
Qingfeng Wang
;
Sameer Pendharkar
;
Binghua Hu
;
Bill Russell
;
Pam Jones-Williams
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
关键词:
Shallow Trench Isolation (STI);
P-body;
Pinch Resistor;
Depth;
Etest;
Monitor;
17.
Novel parameter extraction method for low field drain current of nano-scaled MOSFETs
机译:
纳米MOSFET低场漏电流的新型参数提取方法
作者:
Takuji Tanaka
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2007年
18.
Characterization and Model Parameter Extraction of Symmetrical Centre Tapped Inductor using Build in Mixed Mode and Pure Differential S-Parameters
机译:
用混合模式和纯差分S参数构建对称中心螺纹电感器的表征和模型参数提取
作者:
F. Gianesello
;
Y. Morandini
;
S. Boret
;
D. Gloria
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2009年
19.
Test Structure to Extract Circuit Models of Nanostructures Operating at High Frequencies
机译:
测试结构提取高频工作的纳米结构电路模型
作者:
Francisco R. Madriz
;
John. R. Jameson
;
Shoba Krishnan
;
Xuhui Sun
;
Cary Y. Yang
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2009年
20.
Conference Author Index
机译:
会议作者索引
作者:
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
21.
Experiences In Extraction Of Contact Parameters From Process Evaluation Test-structures
机译:
从过程评估测试结构提取接触参数的经验
作者:
Lieneweg U.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
22.
Method For Accurate Determinaton Of The Intrinsic Cut-off Frequency of IC Bipolar Transistors
机译:
精确确定IC双极晶体管内在截止频率的方法
作者:
Celi D.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
23.
Test Vehicle For The Measurement Of Charge Collection And Soft Error rate Prediction In high-density Memories due to /spl alpha/-particle strikes
机译:
由于/ SPLα/ -Particle罢工,在高密度存储器中测量电荷收集和软错误率预测的测试车辆
作者:
Oldiges P.
;
Furuyama T.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
24.
A Direct Method For Measuring The Gate Oxide Capwi-hnces Of MOSFETS
机译:
用于测量MOSFET栅极氧化物CAPWI-HNCS的直接方法
作者:
Allen R.A.
;
Pina C.A.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
25.
A developmental expert system for test structure ata evaluation
机译:
测试结构ATA评估的发展专家系统
作者:
Linholm L.W.
;
Khera D.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
26.
Defect Diagnostic Matrix -a Defect Learning Vehicle For Submicron Technologies
机译:
缺陷诊断矩阵-A亚微米技术的缺陷学习车辆
作者:
Newhart R.E.
;
Sprogis E.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
27.
Interpretation of capacitance-voltage curves for process fault diagnosis: a machine-learning expert system approach
机译:
处理故障诊断电容 - 电压曲线的解释:一种机器学习专家系统方法
作者:
Walls J.A.
;
Walton A.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
28.
Ring Oscillator Structure For realistic Dynamic Stress Of MOSFETS And Interconnects
机译:
环形振荡器结构,用于MOSFET的现实动态应力和互连
作者:
Winnerl J.
;
Neppl F.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
29.
CMOS Process Monitor
机译:
CMOS Process Monitor.
作者:
Buehler M.G.
;
Linholm L.W.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
30.
1988 Ieee International Conference On Microelectronic Test Structures (ICMTS)
机译:
1988 IEEE微电子测试结构国际会议(ICMTS)
作者:
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
31.
Measurement Of Static Noise Immunity For STL And ISL Bipolar Logics
机译:
STL和ISL双极逻辑静态噪声抗扰度的测量
作者:
Chateau J.M.
;
Depey M.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
32.
Determination Of The HF Model Parameters Of The MOS Transistor By Using Standard Dropin Test Structures
机译:
使用标准滴素测试结构确定MOS晶体管的HF模型参数
作者:
Vandeloo P.
;
Sansen W.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
33.
/spl Delta/L Extraction Using Parasitic Bipolar Transistors
机译:
/ SPL DELTA / L使用寄生双极晶体管提取
作者:
Wilson D.
;
Walton A.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
34.
Temperature Control In Wafer-level Testing Of Large Multi-segment Electromigration Test Structures
机译:
大型多段电迁移测试结构的晶片级测试中的温度控制
作者:
Zamani N.
;
Yu-sang Lin
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
35.
MOS-IC Process And Device Characterization Within Philips
机译:
飞利浦中的MOS-IC过程和设备表征
作者:
Swaving S.
;
Ketting A.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
36.
A Microelectronic Test Structure For Thickness Determination Of Homogeneous Conducting Thin Films In VLSI Processing
机译:
一种微电子测试结构,用于厚度测定VLSI加工中均匀导电薄膜
作者:
Kim J.S.
;
Linholm L.W.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
37.
Expert System For Test Structure Data Interpretation
机译:
测试结构数据解释专家系统
作者:
Montijn-Dorgelo F.N.H.
;
ter Horst H.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
38.
An Objective Method Of Assessing Metal Patterning Quality
机译:
一种评估金属图案化质量的客观方法
作者:
Stevenson J.T.M.
;
Gow J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
39.
New applications of cross-talk-based capacitance measurements CMOS ICs
机译:
基于串扰的电容测量的新应用CMOS IC
作者:
Vendrame L.
;
Bortesi L.
;
Bogliolo A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
integrated circuit measurement;
integrated circuit noise;
capacitance measurement;
CMOS integrated circuits;
coupled circuits;
integrated circuit interconnections;
cross-talk-based capacitance measurement;
charge-based capacitance measurement;
CMOS CBCM transducers;
cross-coupling capacitances;
mismatch measurement;
stacked metal-metal capacitor pairs;
wire interruption localization;
on-chip wiring capacitances;
40.
EOT measurement for ultra-thin gate dielectrics using LC resonance circuit MOS devices
机译:
使用LC谐振电路MOS器件的超薄栅极电介质的EOT测量
作者:
Teramoto A.
;
Komura M.
;
Kuroda R.
;
Watanabe K.
;
Sugawa S.
;
Ohmi T.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
thickness measurement;
dielectric thin films;
circuit resonance;
MIS devices;
leakage currents;
equivalent circuits;
semiconductor device measurement;
EOT measurement;
ultra-thin gate dielectrics;
LC resonance circuit;
MOS devices;
LC resonance method;
large leakage current dielectrics;
external inductance;
external resistance;
equivalent electrical circuit;
resonance impedance-frequency characteristics;
DC gate current/voltage characteristics;
10 to 1 nm;
41.
A self heating test structure using poly resistors and P/sup +//N diodes to characterize anomalous charge transfers in embedded flash memories
机译:
使用多电阻器和P / SUP + // N二极管自加热测试结构,以表征嵌入式闪存中的异常电荷转移
作者:
Mora P.
;
Waltz P.
;
Renard S.
;
Candelier P.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
flash memories;
embedded systems;
resistors;
semiconductor diodes;
self heating test structure;
poly resistors;
P/sup +//N diodes;
anomalous charge transfers;
embedded flash memories;
calibration;
time accuracy;
data retention;
42.
Physical Meaning of a Value Estimated with V{sub}(TH) Mismatch Evaluation Circuit
机译:
用V {SUB}(TH)不匹配评估电路估计值的物理含义
作者:
Kazuo Terada
;
Tomonari Yamauchi
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
43.
Test chip for inductance characterization and modeling for sub-100nm X architecture and Manhattan chip design
机译:
亚100nm X架构和曼哈顿芯片设计的电感表征测试芯片
作者:
Arora N.D.
;
Li Song
;
Shah S.
;
Sinha A.
;
Chang V.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
inductance measurement;
integrated circuit measurement;
integrated circuit modelling;
integrated circuit design;
integrated circuit interconnections;
copper;
aluminium;
CMOS integrated circuits;
VLSI;
S-parameters;
skin effect;
chemical mechanical polishing;
inductance characterization;
inductance modeling;
X architecture chip design;
Manhattan chip design;
on-chip interconnect inductance measurement;
CMOS VLSI chip;
inductive effects;
inductive return paths;
substrate return paths;
co-planar structures;
power grids;
random structures;
S parameter measurements;
wire inductance extraction;
skin effect;
CMP dummy metal fills;
90 nm;
130 nm;
Cu;
Al;
44.
A failure analysis test structure for deep sub-micron CMOS copper interconnect technologies
机译:
深亚微米CMOS铜互连技术的故障分析测试结构
作者:
Cabrini A.
;
Cantarelli D.
;
Cappelletti P.
;
Casiraghi R.
;
Iezzi D.
;
Maurelli A.
;
Pasotti M.
;
Rolandi P.L.
;
Torelli G.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
copper;
integrated circuit testing;
integrated circuit interconnections;
failure analysis;
CMOS integrated circuits;
integrated circuit yield;
integrated circuit reliability;
statistical distributions;
failure analysis test structure;
CMOS interconnect technologies;
manufacturing yield;
circuit reliability;
contacts;
vias;
metal lines;
integration process scaling;
open failures statistical distribution;
interconnect fault location;
130 nm;
Cu;
45.
On-wafer radiation pattern measurements of integrated antennas on standard BiCMOS and glass processes for 40-80GHz applications
机译:
用于40-80GHz应用的标准BICMOS和玻璃工艺上集成天线的晶圆辐射图案测量
作者:
Segura N.
;
Montusclat S.
;
Person C.
;
Tedjini S.
;
Gloria D.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
millimetre wave antennas;
antenna radiation patterns;
antenna testing;
BiCMOS integrated circuits;
S-parameters;
dipole antennas;
microstrip antennas;
on-wafer radiation pattern measurements;
integrated antennas;
glass processes;
BiCMOS;
S-parameter measurements;
CPS dipole dipole antenna;
patch antenna;
integrated millimeterwave antennas;
test bench;
wideband high frequency dipole modeling;
40 to 80 GHz;
46.
Capacitance characterization in integrated circuit development: the intimate relationship of test structure design, equivalent circuit and measurement methodology
机译:
集成电路开发中的电容特性:测试结构设计,等效电路和测量方法的亲密关系
作者:
Brown G.A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
capacitance measurement;
integrated circuit design;
integrated circuit measurement;
integrated circuit testing;
equivalent circuits;
integrated circuit modelling;
dielectric thin films;
IC capacitance characterization;
test structure design;
equivalent circuit;
capacitance measurement methodology;
EOT C-V characterization;
ultra-thin leaky dielectrics;
47.
A test structure for spatial analysis of hot-carrier-induced photoemission in n-MOSFET
机译:
N-MOSFET热载波诱导光曝光的空间分析的试验结构
作者:
Matsuda T.
;
Tanaka T.
;
Iwata H.
;
Ohzone T.
;
Yamashita K.
;
Koike N.
;
Tatsuuma K.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOSFET;
semiconductor device measurement;
semiconductor device reliability;
hot carriers;
photoemission;
hot-carrier effects;
reliability;
photoemission 2D spatial analysis;
n-MOSFET;
hot-carrier-induced photoemission;
photoemission intensity profiles;
gate width direction intensity profiles;
photoemission intensity peak position determination;
peak position variation measurement;
LDD region peak;
peak gate edge distance;
20 to 30 nm;
48.
An improved LDMOS transistor model that accurately predicts capacitance for all bias conditions
机译:
一种改进的LDMOS晶体管模型,可准确预测所有偏置条件的电容
作者:
Frere S.F.
;
Moens P.
;
Desoete B.
;
Wojciechowski D
;
Walton A.J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MIS devices;
equivalent circuits;
semiconductor device models;
hardware description languages;
SPICE;
capacitance;
LDMOS transistor model;
capacitance;
bias conditions;
SPICE macro-model;
DC regime;
AC regime;
standard elements;
Verilog-A modules;
simulator independent model;
49.
Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC
机译:
深NWELL(DNW)隔离130nm及超出SOC的芯片闪烁噪声的表征和模型
作者:
Yang M.T.
;
Kuo D.C.W.
;
Kuo C.W.
;
Wang Y.J.
;
Ho P.P.C.
;
Yeh T.J.
;
Liu S.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
flicker noise;
integrated circuit noise;
isolation technology;
system-on-chip;
integrated circuit measurement;
integrated circuit modelling;
semiconductor device measurement;
semiconductor device models;
radiofrequency integrated circuits;
CMOS integrated circuits;
mixed analogue-digital integrated circuits;
on-chip flicker noise;
deep N-well isolation;
DNW;
SOC;
MS/RF CMOS technology;
wireless system-on-a-chip;
analog node substrate coupling suppression;
digital clock noise;
0.13 micron;
130 nm;
50.
Multi-purpose EM test structure with electrical verification of the failure spot demonstrated using SWEAT for fast wafer level reliability monitoring
机译:
多功能EM测试结构具有电气验证的故障位置,使用汗水用于快速晶片级可靠性监控
作者:
Pietsch A.
;
Martin A.
;
Fazekas J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
semiconductor device reliability;
integrated circuit reliability;
integrated circuit testing;
electromigration;
multi-purpose EM test structure;
electrical verification;
failure spot;
SWEAT;
fast wafer level reliability monitoring;
electromigration test structure;
failure modes;
failure location;
51.
A novel test fixture with enhanced signal port isolation capability for on-wafer microwave measurements
机译:
一种具有增强的信号端口隔离能力的新型测试夹具,用于晶片微波测量
作者:
Kaija T.
;
Ristolainen E.O.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
fixtures;
test equipment;
microwave measurement;
integrated circuit testing;
CMOS integrated circuits;
test fixture;
signal port isolation capability;
on-wafer microwave measurements;
shield-based fixture;
conventional fixture;
open in-fixture performance;
dummy de-embedding;
parasitic components;
20 GHz;
0.35 micron;
52.
Charge Pumping at Radio Frequencies
机译:
电荷泵送在无线电频率下
作者:
G. T. Sasse
;
H. de Vries
;
J. Schmitz
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
53.
Physical meaning of /spl sigma/ value estimated with V/sub TH/-mismatch evaluation circuit
机译:
用v / sub / mismismatch评估电路估计/ spl sigma /值的物理含义
作者:
Terada K.
;
Yamauchi T.
;
Ueki A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
electric potential;
MOSFET circuits;
integrated circuit design;
test equipment;
circuit testing;
semiconductor device testing;
statistical analysis;
test chip;
threshold voltage standard deviation;
test circuit;
MOSFET;
54.
Charge pumping at radio frequencies MOSFET device interface state density measurement
机译:
电荷泵送在无线电频率MOSFET器件接口状态密度测量
作者:
Sasse G.T.
;
de Vries H.
;
Schmitz J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOSFET;
semiconductor device measurement;
interface states;
leakage currents;
dielectric thin films;
electric current measurement;
RF charge pumping;
MOSFET devices;
interface state density measurement;
high leakage current dielectrics;
charge pump current measurement;
ultra thin dielectrics;
2 GHz;
500 MHz;
55.
Accelerated life time estimation of electrostatic microactuators
机译:
静电微致动器的加速终生命估算
作者:
Caillard B.
;
Mita Y.
;
Fukuta Y.
;
Shibata T.
;
Fujita H.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
electrostatic actuators;
high-voltage techniques;
capacitance;
sputter etching;
silicon-on-insulator;
life testing;
electrostatic microactuators;
very low frequency electrical detection;
failures;
high voltage testing;
mean time before failure;
driving voltage;
parallel capacitances;
deep RIE etching;
SOI wafers;
MEMS actuators;
accelerated life time measurement;
56.
Design and characterization of a post-processed copper heat sink for smart power drivers lateral nDMOS drivers
机译:
智能电力驱动器后处理铜散热器的设计与表征侧面NDMOS驱动器
作者:
Van den bosch G.
;
Webers T.
;
Driessens E.
;
Elattari B.
;
Wojciechowski D.
;
Gassot P.
;
Moens P.
;
Groeseneken G.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
copper;
power MOSFET;
heat sinks;
thermal management (packaging);
power integrated circuits;
electroplated coatings;
semiconductor device models;
integrated MOSFET switches;
lateral nDMOS drivers;
post-processed heat sink;
smart power drivers;
electroplating;
large area power drivers;
thermal management;
heat sink efficiency;
energy capability measurements;
electro-thermal simulation;
driver area reduction;
25 micron;
Cu;
57.
Recent trends in reliability assessment of advanced CMOS technologies
机译:
高级CMOS技术可靠性评估的最新趋势
作者:
Groeseneken G.
;
Degraeve R.
;
Kaczer B.
;
Roussel P.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MIS devices;
semiconductor device models;
semiconductor device reliability;
reliability assessment;
advanced CMOS technologies;
reliability lifetime prediction;
failure mechanisms;
oxide breakdown;
chip failure criteria;
failure specifications;
58.
Determination Of Process-dependent Critical SPICE Parameters For Application-specific ICs
机译:
用于应用特定IC的过程依赖性临界分料参数的确定
作者:
Sheu B.J.
;
Chung-Ping Wan
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
59.
Interconnect capacitance characterization for mos-ic process and circuit design
机译:
MOS-IC工艺和电路设计的互连电容特性
作者:
Kortekaas C.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
60.
Comb/serpentine/cross-bridge Test Structure For Fabrication Process Evaluation
机译:
制造过程评估的梳理/蛇形/跨桥测试结构
作者:
Sayah H.R.
;
Buehler M.G.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
61.
An Electrical Test Structure For Measuring Contact Size
机译:
用于测量接触尺寸的电气测试结构
作者:
Freeman G.
;
Lukaszek W.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
62.
Guidelines For Latch-up Characterization Techniques
机译:
闩锁表征技术的指导方针
作者:
Reczek W.
;
Pribyl W.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
63.
Test Circuit Structures For Characterizing The Effects Of Localized Hot-carrier-induced Charge In VLSI Switching Circuits
机译:
测试电路结构,用于表征局部热载波诱导电荷在VLSI开关电路中的影响
作者:
Suehle J.S.
;
Galloway K.F.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
64.
Evaluating Integrated Circuit Technologles For Space Application - The GVSC Test Chip
机译:
评估空间应用的集成电路技术 - GVSC测试芯片
作者:
Wilson K.T.
;
Zietlow T.C.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
65.
A Novel Device Structure For Studying Gate And Channel Edge Effects In IGFET's
机译:
用于研究IGFET的门和频道边缘效应的新型设备结构
作者:
Serack J.A.
;
Walton A.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
66.
Thermal Interactions Between Electromigration Test Structures
机译:
电迁移测试结构之间的热相互作用
作者:
Schafft H.A.
;
Albers J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
67.
Impact Of The Self-heating Effect On Circuit Performance Estimation Using DC Model Parameters
机译:
自加热效应对电路性能估计的影响使用直流模型参数
作者:
Takace D.
;
Trager J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
68.
Sources Of Error In Extracting The Specific Contact Resistance From Kelvin Device Measurements
机译:
从开尔文设备测量中提取特定接触电阻的误差源
作者:
Alexander W.J.C.
;
Walton A.J.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
69.
A Fully Analytical MOSFET Model Parameter Extraction Approach
机译:
完全分析MOSFET模型参数提取方法
作者:
Tuinhout H.P.
;
Swaving S.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
70.
Spatially Non-uniform, Time Varying Thermal Characterization Of VlSI Chips
机译:
空间不均匀,随时间变化的VLSI芯片的热表征
作者:
Cooke B.J.
;
Prince J.L.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
71.
Total Dose Radiation Respnse Of Test Structures And VLSI Lcqic Devices: An Analytical And Experimental Correlation
机译:
测试结构和VLSI逻辑器件的总剂量辐射响应:分析与实验相关性
作者:
Newberry D.M.
;
Peters B.E.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
72.
Standard Defect Monitor
机译:
标准缺陷监视器
作者:
Weber C.
;
Institute of Electric and Electronic Engineer
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2001年
73.
A novel mobility-variation-free extraction technique of capacitance coupling coefficient for stacked flash memory cell
机译:
一种新的堆叠闪存单元电容耦合系数的新型移动变化提取技术
作者:
Okagaki T.
;
Tanizawa M.
;
Fujinaga M.
;
Kunikiyo T.
;
Yuki H.
;
Ishikawa K.
;
Nishikawa Y.
;
Eimori T.
;
Inuishi M.
;
Oji Y.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
integrated circuit testing;
integrated circuit measurement;
capacitance measurement;
flash memories;
process monitoring;
charge based capacitance measurement;
mobility-variation-free extraction technique;
control gate capacitance coupling coefficient;
stacked flash memory cell;
test patterns;
CBCM method;
floating gate connected capacitances measurement;
TCAD;
channel current characteristics;
process monitoring;
74.
Test structure for performance evaluation of 3 dimensional FinFETs
机译:
3维FinFET性能评估的测试结构
作者:
Young Joon Ahn
;
Hye Jin Cho
;
Hee Soo Kang
;
Choong-Ho Lee
;
Chul Lee
;
Jae-man Yoon
;
Tae Yong Kim
;
Eun Suk Cho
;
Suk-kang Sung
;
Donggun Park
;
Kinam Kim
;
Byung-Il Ryu
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOSFET;
silicon;
test structure;
performance evaluation;
3 dimensional FinFET;
3D MOSFET;
planar MOSFET;
Si orientation;
surface channel;
reliability evaluation;
3D FinFET;
75.
Suspended Greek cross test structures for measuring the sheet resistance of non-standard cleanroom materials
机译:
悬浮的希腊交叉试验结构,用于测量非标准洁净室材料的薄层电阻
作者:
Enderling S.
;
Brown C.L. III
;
Smith S.
;
Dicks M.H.
;
Stevenson J.T.M.
;
Ross A.W.S.
;
Mitkova M.
;
Kozicki M.N.
;
Walton A.J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
electric resistance measurement;
gold;
suspended Greek cross test structures;
sheet resistance measurement;
nonstandard cleanroom materials;
CMOS process incompatible materials;
cross structure arm widths;
resistivity extraction;
blanket deposited films;
4.85/spl times/10/sup -8/ ohmm;
3.0/spl times/10/sup -8/ to 5.0/spl times/10/sup -8/ ohmm;
5 to 20 micron;
Au;
76.
Novel realistic short structure construction for parasitic resistance de-embedding and on-wafer inductor characterization
机译:
寄生电阻去嵌入和晶圆电感器表征的新型逼真短结构施工
作者:
Tao J.
;
Findley P.
;
Rezvani G.A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
inductors;
S-parameters;
Q-factor;
inductance;
electric resistance;
radiofrequency integrated circuits;
characteristics measurement;
CMOS integrated circuits;
inductance measurement;
electric resistance measurement;
realistic short structure construction;
parasitic resistance de-embedding;
on-wafer inductor characterization;
S-parameters;
through structure;
Z-parameters;
inductor parameters;
CMOS design;
RFIC;
77.
A novel CBCM method free from charge injection induced errors: investigation into the impact of floating dummy-fills on interconnect capacitance
机译:
一种新的CBCM方法,没有充电注射诱导的误差:调查浮动虚拟填充对互连电容的影响
作者:
Chang Y.W.
;
Chang H.W.
;
Lu T.C.
;
King Y.
;
Ting W.
;
Ku J.
;
Lu C.Y.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
capacitance measurement;
integrated circuit interconnections;
integrated circuit measurement;
charge injection;
circuit optimisation;
crosstalk;
integrated circuit design;
charge-based capacitance measurement;
interconnect characterization;
CBCM method;
charge injection induced error free method;
floating dummy-fill effects;
interconnect capacitance;
CIEF;
chip performance optimization;
crosstalk minimization;
dummy pattern design;
78.
Mismatch characterisation of chip interconnect resistance
机译:
芯片互连电阻的不匹配表征
作者:
Deveugele J.
;
Libin Yao
;
Steyaert M.
;
Sansen W.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
resistors;
integrated circuit interconnections;
analogue integrated circuits;
electric resistance;
chip interconnect resistance mismatch characterisation;
analog circuits;
matched resistors;
resistive elements;
0.18 micron;
79.
Parameter variation on chip-level
机译:
芯片级参数变化
作者:
Schaper U.
;
Einfeld J.
;
Sauerbrey A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOS integrated circuits;
integrated circuit testing;
process monitoring;
statistical analysis;
semiconductor device measurement;
chip-level parameter variation;
integrated MOSFET circuits;
circuit building blocks;
circuit features;
device parameters;
global scale;
wafer scale;
local scale;
close-packed device pairs;
intra-die-statistics;
process control monitoring;
matching characterization;
test keys;
80.
Impact of mask alignment on the tunneling field effect transistor (TFET)
机译:
掩模对准对隧道场效应晶体管(TFET)的影响
作者:
Nirschl T.
;
Schaper U.
;
Einfeld J.
;
Henzler S.
;
Sterkel M.
;
Singer J.
;
Fulde M.
;
Hansch W.
;
Georgakos G.
;
Schmitt-Landsiedell D.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
tunnelling;
field effect transistors;
masks;
doping profiles;
semiconductor device measurement;
quantum-mechanical device;
p-implant mask alignment;
tunneling field effect transistor;
TFET;
CMOS process flow compatible device;
short channel characteristics;
low static power consumption;
source extension overlapping p-implant layer;
81.
A study of 90nm MOSFET subthreshold hump characteristics using newly developed MOSFET array test structure
机译:
使用新开发的MOSFET阵列测试结构研究90nm MOSFET亚阈值驼峰特性
作者:
Mizumura A.
;
Ohishi T.
;
Yokoyama N.
;
Nonaka M.
;
Tanaka S.
;
Ammo H.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOSFET;
semiconductor device testing;
leakage currents;
production yield enhancement;
early process definition;
MOSFET subthreshold hump characteristics;
MOSFET array test structure;
small-scale DUT layout pattern;
gate leakage;
off leakage;
subthreshold slope;
hump occurrence percentage;
MOSFET array hump variation;
standby-current;
logic LSI chips;
90 nm;
82.
Improved test structures for the electrical measurement of feature size on an alternating aperture phase-shifting mask
机译:
改进的测试结构在交流孔相移掩模上的特征尺寸的电测量
作者:
Smith S.
;
Walton A.J.
;
McCallum M.
;
Hourd A.C.
;
Stevenson J.T.M.
;
Ross A.W.S.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
phase shifting masks;
size measurement;
electric resistance measurement;
atomic force microscopy;
phase-shifting mask test structures;
feature size electrical measurement;
alternating aperture phase-shifting mask;
Greek cross structures;
sheet resistance extraction;
linewidth structure measurement;
critical dimension offset variability reduction;
phase-shifting elements;
atomic force microscope measurements;
83.
Simple modeling expressions for substrate network of on-chip inductors
机译:
片上电感器基板网络的简单建模表达
作者:
Lai I.C.H.
;
Fujishima M.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
thin film inductors;
equivalent circuits;
integrated circuit modelling;
CMOS integrated circuits;
silicon-on-insulator;
Q-factor;
inductor equivalent circuit model;
monomial expression;
on-chip spiral inductors;
on-chip inductor substrate network;
inductor geometry parameters;
3D field solver;
CMOS process;
SOI;
Q-factor;
amplifier simulation;
IP3 estimation;
RFIC;
0.35 micron;
0.15 micron;
84.
A test structure to measure sheet resistances of highly-doped-drain and lightly-doped-drain in CMOSFET
机译:
测量CMOSFET中高掺杂漏极和轻掺杂排出的薄层电阻的测试结构
作者:
Ohzone T.
;
Okada K.
;
Morishita T.
;
Komoku K.
;
Matsuda T.
;
Iwata H.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
MOSFET;
electric resistance measurement;
test structure;
sheet resistances;
highly doped drain;
lightly doped drain;
LDD-type CMOSFET;
source/drain-resistance reciprocal;
85.
RF monitoring test structures for advanced RF technologies working up to 100GHz with less than 80/spl mu/m width
机译:
RF监控高级RF技术的测试结构,工作高达100GHz,宽度小于80 / SPL宽度
作者:
Perrotin A.
;
Gloria D.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
monitoring;
radiofrequency integrated circuits;
integrated circuit testing;
silicon;
RF monitoring;
RF test structure;
advanced RF technologies;
advanced silicon technologies;
reduced scribe line dimensions;
device RF matching parameters;
86.
Comparison of SEM and HRTEM CD measurements extracted from test-structures having feature linewidths from 40 nm to 240 nm
机译:
从40nm到240nm的特征线宽提取的SEM和HRTEM CD测量的比较
作者:
Cresswell M.W.
;
Park B.
;
Allen R.A.
;
Guthrie W.F.
;
Dixson R.G.
;
Tan W.M.
;
Murabito C.E.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
size measurement;
measurement uncertainty;
scanning electron microscopy;
transmission electron microscopy;
transfer standards;
calibration;
CD-uncertainty analysis;
SEM CD measurements;
HRTEM CD measurements;
test structure feature linewidths;
critical dimension measurements;
scanning electron microscope images;
high resolution transmission electron microscopy images;
monocrystalline silicon features;
CD-metrology;
SEM transfer-metrology calibration statistics;
CD reference material calibration;
40 to 240 nm;
Si;
87.
New extraction method for gate bias dependent series resistance in nanometric double gate transistors
机译:
纳米双栅极晶体管栅极偏置梯级串联电阻的新提取方法
作者:
Cros A.
;
Harrison S.
;
Cerutti R.
;
Coronel P.
;
Ghibaudo G.
;
Brut H.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
field effect transistors;
semiconductor device measurement;
semiconductor device models;
electric resistance measurement;
nanoelectronics;
carrier mobility;
gate bias dependent series resistance;
series resistance extraction method;
nanometric double gate transistors;
extrinsic mobility reduction parameters;
gate bias voltage dependent resistance;
low field parameters;
high field parameters;
gate-all-around transistors;
doped body transistors;
undoped body transistors;
88.
Speed - accuracy trade-off for measurement and characterization of the matching performance of SiGe:C HBTs, applied to a 200 GHz technology
机译:
Sige:C HBTS匹配性能测量和表征的速度 - 精度折衷速度:C HBT,适用于200 GHz技术
作者:
Choi L.J.
;
Venegas R.
;
Decoutere S.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
Ge-Si alloys;
semiconductor materials;
carbon;
semiconductor device measurement;
heterojunction bipolar transistors;
electric current measurement;
millimetre wave bipolar transistors;
emitter resistance;
speed/accuracy trade-off;
HBT characterization;
matching performance measurement;
HBT dimensions;
HBT biasing conditions;
low current region;
high current region;
bipolar current mismatch bias dependence;
200 GHz;
SiGe:C;
89.
A simple and accurate capacitance ratio measurement technique for integrated circuit capacitor arrays
机译:
集成电路电容器阵列的简单准确的电容比测量技术
作者:
Zhenqiu Ning
;
De Schepper L.
;
Delecourt H.-X.
;
Gillon R.
;
Tack M.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
capacitance measurement;
integrated circuit testing;
characteristics measurement;
integrated circuit design;
CMOS analogue integrated circuits;
capacitance ratio measurement technique;
integrated circuit capacitor arrays;
analogue circuits;
floating-gate AC nulling technique;
test-structure;
binary-weighted capacitor array;
test chip design;
CMOS technologies;
90.
High speed test structures for in-line process monitoring and model calibration CMOS applications
机译:
用于在线过程监控和模型校准的高速测试结构CMOS应用
作者:
Ketchen M.
;
Bhushan M.
;
Pearson D.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
CMOS integrated circuits;
integrated circuit testing;
process monitoring;
logic gates;
calibration;
high speed test structures;
in-line process monitoring;
model calibration;
CMOS gates;
DC I/O test structures;
parametric testers;
ring oscillators;
self-consistent parameter extraction;
circuit delays;
gate length;
leakage components;
self-timed calibrated structure;
SOI switching history effects;
self-generated pulses;
100 ps;
91.
Verification of layout efficient shield-based de-embedding techniques for on-wafer HBT characterisation up to 30 GHz
机译:
验证布局高效的基于屏蔽的去嵌入技术,用于晶圆上的晶圆HBT表征高达30 GHz
作者:
OSullivan J.A.
;
McCarthy K.G.
;
Murphy A.C.
;
Murphy P.J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
heterojunction bipolar transistors;
millimetre wave bipolar transistors;
semiconductor device measurement;
shielding;
layout efficient shield-based de-embedding techniques;
on-wafer HBT characterisation;
on-wafer measurements;
MOSFET;
shield-based deembedding structures;
extrinsic parasitic effects;
layout-area requirements reduction;
30 GHz;
92.
Extraction of critical dimension reference feature CDs from new test structure using HRTEM imaging
机译:
利用HRTEM成像从新测试结构提取关键尺寸参考特征CD
作者:
Allen R.A.
;
Hunt A.
;
Murabito C.E.
;
Park B.
;
Guthrie W.F.
;
Cresswell M.W.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
size measurement;
length measurement;
lattice constants;
transmission electron microscopy;
specimen preparation;
measurement uncertainty;
lattice counting procedure;
critical dimension reference feature extraction;
test structure CD measurement;
CD reference materials;
silicon (111) lattice spacing linewidth reference;
high-resolution transmission electron microscopy;
HRTEM sample preparation;
fringe counting procedures;
measurement uncertainties;
feature width;
100 nm;
40 nm;
93.
RF-ESD design and measurement of CMOS LNAs: a comparison between diode and inductive protection
机译:
CMOS LNA的RF-ESD设计和测量:二极管和电感保护之间的比较
作者:
Leroux P.
;
Steyaert M.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
electrostatic discharge;
protection;
CMOS analogue integrated circuits;
integrated circuit design;
semiconductor device measurement;
radiofrequency amplifiers;
radio equipment;
RF-ESD-protection;
CMOS LNA;
diode protection;
inductive protection;
CMOS low-noise amplifiers;
noise figure;
power gain;
GPS L1 band;
wireless LAN applications;
HBM specification;
human body model ESD stress;
1.57 GHz;
1.3 dB;
16.5 dB;
5 GHz;
20 dB;
3.5 dB;
2 kV;
94.
MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances
机译:
65nm技术的MOSFET匹配改进,为模拟和SRAM表演提供增益
作者:
Difrenza R.
;
Rochereau K.
;
Devoivre T.
;
Tavel B.
;
Duriez B.
;
Roy D.
;
Jullian S.
;
Dezzani A.
;
Boulestin R.
;
Stolk P.
;
Arnaud F.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
CMOS analogue integrated circuits;
CMOS memory circuits;
MOSFET;
SRAM chips;
doping profiles;
ADC;
DAC;
CMOS technology;
gate process optimization;
MOSFET matching;
SRAM;
LDD concentration;
thermal budget;
halo implant;
gate impact reduction;
NMOS;
PMOS;
cell read current;
analog IC linearity;
analog IC resolution;
65 nm;
95.
Experimental analysis of a Ge-HfO/sub 2/-TaN gate stack with a large amount of interface states
机译:
具有大量接口状态的GE-HFO / SUB 2 / -TAN栅极堆栈的实验分析
作者:
Croon J.A.
;
Kaczer B.
;
Lujan G.S.
;
Kubicek S.
;
Groeseneken G.
;
Meuris M.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
germanium;
hafnium compounds;
tantalum compounds;
interface states;
MOS capacitors;
substrates;
semiconductor device measurement;
MOSFET;
electrical faults;
characteristics measurement;
germanium substrate;
hafnium oxide;
tantalum nitride;
gate stack;
interface states;
MOS capacitors;
gated diodes;
conductance analysis;
p-substrate capacitors;
n-substrate capacitors;
junction leakage;
Ge-HfO/sub 2/-TaN;
96.
Substrate isolation in 0.18um CMOS technology
机译:
0.18um CMOS技术的衬底隔离
作者:
Rezvani G.A.
;
Jon Tao
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
integrated circuit measurement;
radiofrequency integrated circuits;
CMOS integrated circuits;
isolation technology;
S-parameters;
integrated circuit noise;
coupled circuits;
mixed analogue-digital integrated circuits;
RFIC;
CMOS technology substrate isolation;
deep n-well isolation;
DNW;
guard ring;
substrate contact size;
substrate proximity;
S21 isolation measure;
junction diode noise source;
noise pick up sensor;
substrate coupling reduction;
SOI;
0.18 micron;
97.
Extraction of time dependent data from time domain reflection transmission line pulse measurements ESD protection design
机译:
从时域反射传输线脉冲测量提取时间依赖数据ESD保护设计
作者:
Ashton R.A.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
time-domain reflectometry;
integrated circuit measurement;
semiconductor device measurement;
voltage measurement;
electric current measurement;
pulse measurement;
electrostatic discharge;
time dependent voltage measurements;
time dependent current measurements;
time dependent data extraction;
time domain reflection transmission line pulse measurements;
ESD protection design;
TLP system;
98.
Substrate Isolation in 0.18μm CMOS Technology
机译:
0.18μmCMOS技术中的衬底隔离
作者:
G. Ali Rezvani
;
Jon Tao
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
99.
Design and implementation of an ultra high precision parametric mismatch measurement system
机译:
超高精度参数失配系统的设计与实现
作者:
Ewert T.
;
Tuinhoutt H.
;
Wils N.
;
Olsson J.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
characteristics measurement;
semiconductor device measurement;
bipolar transistors;
ultra high precision parametric mismatch measurement system;
parametric mismatch characterization approach;
BJT mismatch measurement;
100.
Measurement of inner-chip variation and signal integrity by a 90-nm large-scale TEG test element group
机译:
通过90-nm大规模teg 测试元素组测量内芯片变化和信号完整性
作者:
Yamamoto M.
;
Hayasi Y.
;
Endo H.
;
Masuda H.
会议名称:
《IEEE International Conference on Microelectronic Test Structures》
|
2005年
关键词:
integrated circuit measurement;
integrated circuit testing;
logic testing;
integrated circuit design;
system-on-chip;
inner-chip variation measurement;
signal integrity measurement;
large-scale TEG;
test element group;
test structure;
SI yield;
logic tester;
address decoder circuit;
large length wire configurations;
phase difference effect;
SoC circuit design;
90 nm;
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