Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

Ravneet Kaur; Rishu Chaujar; Manoj Saxena; R. S. Gupta

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Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

机译：用于混合模式应用的50nm绝缘浅扩展栅堆叠（ISEGaS）MOSFET的性能研究

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An extended study of electrical characteristics of 50-nm single-material-gate insulated-shallow-extension-gate-stack (ISEGaS) MOSFET is performed using ATLAS-2D. Incorporation of dual-material-gate architecture leads to the suppression of short channel effects along with the improvement in device intrinsic gain (gmtimesRout), voltage gain (gm/IDS), and Ion/Ioff ratio, thereby opening a new era of ISEGaS MOSFETs for mixed mode applications

机译：使用ATLAS-2D进行了50nm单材料栅极绝缘浅扩展栅堆叠（ISEGaS）MOSFET的电学特性的扩展研究。结合双材料栅极架构可抑制短沟道效应，并改善器件固有增益（gmtimesRout），电压增益（gm / IDS）和离子/ Ioff比，从而开启了ISEGaS MOSFET的新时代用于混合模式应用

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来源
《IEEE Transactions on Electron Devices》 |2007年第2007期|p.365-368|共4页
作者
Ravneet Kaur; Rishu Chaujar; Manoj Saxena; R. S. Gupta;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
MOSFET; semiconductor device models; 50 nm; ATLAS-2D; ISEGaS; MOSFET; dual-material-gate architecture; energy-balance-transport; insulated-shallow-extension gate-stack transistor; mixed mode applications; short channel effects suppression; single-material-gate tran;

机译：MOSFET;半导体器件模型;50 nm;ATLAS-2D;ISEGaS;MOSFET;双材料栅架构;能量平衡传输;绝缘浅扩展栅堆叠晶体管;混合模式应用;短沟道效应抑制;单个-材料门转换;

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Performance Investigation of 50-nm Insulated-Shallow-Extension Gate-Stack (ISEGaS) MOSFET for Mixed Mode Applications

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