METHOD AND CIRCUIT FOR INVESTIGATING CHARGE TRANSFERRED ARRAY TRANSISTOR CHARACTERISTICS AND AGING UNDER ACTUAL STRESS AND ITS APPLICATION TO DRAM MOSFET ARRAY TRANSISTOR

摘要

PURPOSE: A method and a circuit for investigating the characteristics of a charge transferred transistor and aging under actual stress and its application to a DRAM MOSFET array transistor are provided to measure the amount of transistor charge transfer and NC charge storing capacitor of a DRAM cell. CONSTITUTION: The DRAM cell includes an on-chip voltage amplifier(A), and a DRAM array(8) where only one cell is addressed by controlling a word line WL(1) and a bit line BL(3). A BL sensing logic setting circuit includes three pass gates(PG1,PG2,PG3) and an inverter opening and closing WL and BL to transfer charges by enabling the pass gates selectively. A voltage amplifier amplifies a signal without changing the shape of a pulse but enough to measure it.