Design and Analysis of High Mobility Enhancement-Mode 4H-SiC MOSFETs Using a Thin-SiO₂/Al₂O₃ Gate-Stack

摘要

High-performance 4H-SiC MOSFETs have been fabricated, having a peak effective mobility of 265 cm(2)/V.s, and a peak field effect mobility of 154 cm(2)/V s, in 2-mu m gate length MOSFETs. The gate-stack was designed to minimize interface states and comprised a 0.7-nm thermally grown SiO2 on 4H-SiC, followed by Al2O3 and a metal gate contact. In this way, carbon remaining following SiC oxidation is significantly reduced. A density of interface traps in the range of 6 x 10(11)-5 x 10(10)cm(-2)eV(-1) is also obtained. Temperature-dependent electrical data reveal that the high mobility results from conduction being phonon-limited, rather than Coulomb-limited. Furthermore, universal mobility in these 4H-SiC MOSFETs is shown to be up to 50% of that observed in the Si devices. Expressions for electric field-dependent contributions to mobility are presented. A steep subthreshold slope of 127 mV/decade indicates low electrical defect density. A temperature coefficient of -4.6 mV/K in threshold voltage is similar to that in the Si MOSFETs.