首页> 中文期刊> 《中国集成电路》 >应力技术改善CMOS器件性能研究进展

应力技术改善CMOS器件性能研究进展

         

摘要

随着集成电路技术的快速发展,等比例缩小技术已经不能满足摩尔定律,应变硅金属氧化物硅场效应晶体管(MOSFET)技术成为后硅时代研究的热点。应变硅技术通过拉伸或压缩硅晶格达到器件尺寸不变的情况下,可提高器件性能的目的,同时应变硅技术与传统硅工艺兼容,节约了生产成本。对于应变硅互补金属氧化物硅晶体管(CMOS)器件的性能以及可靠性问题的研究也日益增加。本文通过介绍几种常用的应变技术(应力记忆技术(SMT),锗化硅技术(SiGe),接触孔刻蚀阻挡层(CESL))的应变机理、材料性能和工艺条件对应力技术的影响来探讨以后应力技术的发展趋势。%As the development of integrated circuit, the scaling technology cannot be compatible with the Moore law. As a result,the stressed silicon technology metal-oxide-silicon field effect transistor becomes the research focus of post-silicon era. The stressed silicon technology can improve the performance of device by compressing or drawing with the same size. Thestress technology consume the cost due to it is compatible with existed fabrication process of silicon. At the same time, the studies on performance and reliability of stressed CMOS device increase due to its utility. In this paper, we discuss the developing trend of stress technology by introducing the mechanism of some current stress technologies ( stress memory technology ( SMT ), SiGe technology,contact etch stopping layer ( CESL ) ) and the impact of material properties and process on stress technology.

著录项

相似文献

  • 中文文献
  • 外文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号