Method and structure for improving the variation in device performance in the dual stress liner technique

摘要

To provide a semiconductor structure and method without increasing significantly the overall dimensions of the integrated circuit problems, to overcome the dual stress liner boundary problem. According to the present invention comprises, gap or during dual stress liner boundary is to be placed by force to the dummy gate region on adjacent. By doing place by force or gaps dual stress liner boundary dummy gate region on adjacent high stress associated with the gap or dual stress liner boundary, moves to the dummy gate material instead of the semiconductor substrate. Therefore, the influence of the dual stress liner boundary for FET to nearest neighbor is reduced. Furthermore, the advantage of packing density and device variability is achieved by using the present invention. [Selection Figure 7