Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond

摘要

Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved with SPT. Leading edge PFET I{sub}(on)=660μA/μm at I{sub}(off)=100nA/μm at 1V V{sub}(dd) operation is demonstrated without using embedded SiGe junctions. Inverter ring oscillator delay is reduced by 15% with SPT.