Effect of the Gate Oxide Thickness on the Speed of MOS Integrated Circuits

摘要

A simple analysis is presented for the effect of the gate oxide thickness on the circuit speed in a short-channel CMOS/inverter delay circuit. The present analysis is performed within the first-order theory of the MOS transistor. The result of the analysis shows that an optimum value of the gate oxide thickness exists, beyond which a further scaling of the gate oxide will not improve but degrade the circuit speed. The circuit speed corresponding to this optimum oxide thickness is the ultimate upper limit theoretically possible in a given MOS integrated circuit. The optimum value of the gate oxide thickness, to the first order approximation, is proportional to the channel width W, but it is independent of the channel length L. In particular, for wide channel devices, this optimum value exceeds the 5 nm - 30 nm range, which is of practical significance in the design and processing of advanced VLSI circuits.