首页> 外文期刊>Japanese Journal of Applied Physics. Part 1, Regular Papers & Short Notes >Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current
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Quantum Mechanical Corrected Simulation Program with Integrated Circuit Emphasis Model for Simulation of Ultrathin Oxide Metal-Oxide-Semiconductor Field Effect Transistor Gate Tunneling Current

机译:具有集成电路重点模型的量子力学校正仿真程序,用于仿真超薄氧化物金属氧化物半导体场效应晶体管栅隧穿电流

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In this paper we present a quantum mechanical corrected gate tunneling current model for simulating ultrathin oxide metal oxide-semiconductor (MOS) devices. By approximating the physically based Esaki-Tsu tunneling formula and explicitly modeling the classical (CL) and quantum mechanical (QM) corrected surface potential, this model successfully predicts the gate tunneling current for ultrathin oxide MOS samples under different applied biases. Simply assuming all tunneling electrons have the same kinetic energy, the Esaki-Tsu tunneling formula is first simplified so that it can be solved withoul encountering numerical integral problems. Numerical solutions of the classical Poisson equation and Schroedinger-Poisson equations are then used to analytically express the CL and QM corrected surface potentials explicitly in terms of substrate doping, thickness of the gate oxide (T_(ox)), and applied bias. The full explicit, physical-based, and QM corrected gate tunneling current model quantitatively shows good agreement with the technology computer-aided design (TCAD) simulation. Compared with the measured gate tunneling current from fabricated 0.12 μm n-type Metal-Oxide-Semiconductor Field Elfecl Transistors (NMOSFETs) with three different thicknesses of gate oxide, T_(ox) = 1, 1.2 and 1.5 nm, the QM corrected gate tunneling current model shows good accuracy for various ultrathin oxide samples under different biases. However, the gate tunneling current model with the CL surface potential results in one order of magnitude underestimation in comparison with the measured data. We implement the gate tunneling current model into the simulation program with integrated circuit emphasis (SPICE) simulator and perform a DC simulation. Simulated results preliminarily show the effect of the gate leakage current on the drain current without any numerical convergence problem.
机译:在本文中,我们提出了一种量子机械校正的栅极隧穿电流模型,用于模拟超薄氧化物金属氧化物半导体(MOS)器件。通过近似基于物理的Esaki-Tsu隧穿公式,并明确建模经经典(CL)和量子力学(QM)校正的表面电势,该模型成功预测了在不同施加偏压下超薄氧化物MOS样品的栅极隧穿电流。简单地假设所有隧穿电子都具有相同的动能,则首先简化Esaki-Tsu隧穿公式,以便可以解决遇到数值积分问题的情况。然后,使用经典Poisson方程和Schroedinger-Poisson方程的数值解,根据衬底掺杂,栅极氧化物的厚度(T_(ox))和施加的偏压,明确地表达CL和QM校正的表面电势。完全显式的,基于物理的和QM校正的栅极隧穿电流模型定量地显示了与技术计算机辅助设计(TCAD)仿真的良好一致性。 QM校正后的栅极隧穿与由三种厚度不同的栅极氧化物T_(ox)= 1,1.2和1.5 nm制成的0.12μmn型金属氧化物半导体场效应晶体管(NMOSFET)测得的栅极隧穿电流相比当前模型显示了在不同偏压下各种超薄氧化物样品的良好准确性。但是,与测量数据相比,具有CL表面电势的栅极隧穿电流模型导致被低估了一个数量级。我们使用集成电路重点(SPICE)仿真器将栅极隧道电流模型实现到仿真程序中,并执行DC仿真。仿真结果初步显示了栅极漏电流对漏极电流的影响,没有任何数值收敛问题。

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