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Automation and Test in Europe Conference and Exhibition
Automation and Test in Europe Conference and Exhibition
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1.
Enhanced diameter bounding via structural transformation
机译:
通过结构转换增强直径界限
作者:
Baumgartner J.
;
Kuehlmann A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
formal verification;
computability;
approximation theory;
state-space methods;
enhanced diameter bounding;
structural transformation;
bounded model checking;
BMC;
relative scalability;
diameter overapproximation;
exact diameter calculation;
exponential resources;
redundancy removal;
retiming;
target enlargement;
arbitrary diameter approximation;
2.
Hierarchical automatic behavioral model generation of nonlinear analog circuits based on nonlinear symbolic techniques
机译:
基于非线性符号技术的非线性模拟电路的分层自动行为模型
作者:
Nathke L.
;
Burkhay V.
;
Hedrich L.
;
Barke E.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue circuits;
simulation;
hierarchical systems;
automatic programming;
differential equations;
nonlinear network analysis;
hierarchical automatic behavioral model;
nonlinear analog circuits;
nonlinear symbolic techniques;
simulation time;
procedural model;
formulation approach;
simplification method;
physical transistor properties;
element models;
simplification process;
netlists;
3.
Clock management in a Gigabit Ethernet physical layer transceiver circuit
机译:
千兆以太网物理层收发器电路中的时钟管理
作者:
Diaz J.C.
;
Saburit M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
local area networks;
transceivers;
timing circuits;
mixed analogue-digital integrated circuits;
digital integrated circuits;
clock management;
gigabit Ethernet physical layer transceiver circuit;
mixed signal synchronous circuit;
high speed synchronous circuit;
multiclock synchronous circuit;
MA1111A13 circuit clock distribution;
power reduction;
asynchronous clock domains interoperability;
compatibility;
input-output timing standards;
data rate;
complex clocking scheme;
clock network;
4.
Low static-power frequent-value data caches
机译:
低静功率频繁值数据库
作者:
Chuanjun Zhang
;
Jun Yang
;
Vahid F.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
cache storage;
memory architecture;
integrated circuit design;
low-power electronics;
frequent-value data caches;
static energy dissipation;
cache memories;
microprocessor energy dissipation;
nanoscale technology characteristics;
on-chip caches;
FV;
static cache power;
dynamic cache power;
application-specific cache design;
configuration registers;
Spec 2000 benchmarks;
dynamic power savings;
static energy savings;
5.
Analysis and modeling of energy reducing source code transformations
机译:
能量减少源代码转换的分析与建模
作者:
Brandolese C.
;
Fornaciari W.
;
Salice F.
;
Sciuto D.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
source coding;
power consumption;
optimising compilers;
program control structures;
energy reducing source code transformations;
energy driven source-to-source transformations;
code transformation techniques;
embedded system processors;
embedded software design;
6.
Analyzing on-chip communication in a MPSoC environment
机译:
分析MPSOC环境中的片上通信
作者:
Loghi M.
;
Angiolini F.
;
Bertozzi D.
;
Benini L.
;
Zafalon R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
autoregressive moving average processes;
circuit simulation;
circuit CAD;
system buses;
computer architecture;
on-chip communication;
multiprocessor SoC environment;
multiprocessor systems-on-chip;
communication architecture analysis;
systemC based platform;
cycle accurate level;
signal accurate level;
communication subsystem simulation;
ARM processors;
7.
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA
机译:
评估SEU影响基于SRAM的FPGA的配置存储器的影响
作者:
Bellato M.
;
Bernardi P.
;
Bortolato D.
;
Candelori A.
;
Ceschia M.
;
Paccagnella A.
;
Rebaudengo M.
;
Reorda M.S.
;
Violante M.
;
Zambolin P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
field programmable gate arrays;
SRAM chips;
logic design;
logic testing;
integrated circuit reliability;
radiation effects;
SEU;
SRAM-based FPGA;
single event upsets;
transient faults;
device configuration memory;
radiation testing;
FPGA device;
safety-critical environments;
route strategies;
supporting tools;
programmable logic devices;
ASIC;
field programmable gate arrays;
configurable logic blocks;
8.
Balanced excitation and its effect on the fortuitous detection of dynamic defects
机译:
平衡励磁及其对偶然检测动态缺陷的影响
作者:
Dworak J.
;
Cobb B.
;
Wingfield J.
;
Mercer M.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
automatic test pattern generation;
fault diagnosis;
balanced excitation;
fortuitous detection;
dynamic defects;
automatic test pattern generation;
fault diagnosis;
9.
Task feasibility analysis and dynamic voltage scaling in fault-tolerant real-time embedded systems
机译:
容错实时嵌入式系统中的任务可行性分析和动态电压缩放
作者:
Ying Zhang
;
Chakrabarty K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
task analysis;
fault tolerant computing;
embedded systems;
system recovery;
genetic algorithms;
energy management systems;
task feasibility analysis;
dynamic voltage scaling;
fault tolerant real time embedded systems;
processor speeds;
rollback recovery time;
memory access time;
memory access energy;
checkpointing data;
embedded processors;
genetic algorithms;
energy management systems;
10.
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
机译:
基于模拟的电源感知架构探讨了多处理器系统片式设计
作者:
Menichelli F.
;
Olivieri M.
;
Benini L.
;
Donno M.
;
Bisdounis L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
multiprocessing systems;
system-on-chip;
ad hoc networks;
integrated circuit design;
simulation based power aware architecture;
multiprocessor system-on-chip design;
HIPERLAN/2 communication protocol;
ad-hoc C++ simulation environment;
power model integration;
CPU;
central processing unit;
DMA unit;
direct memory access;
software mapping;
11.
SystemC and SystemVerilog: Where do they fit? Where are they going?
机译:
systemc和systemverilog:它们适合在哪里?他们要去哪?
作者:
Rosenstiel W.
;
Swan S.
;
Ghenassia F.
;
Flake P.
;
Srouji J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware description languages;
SystemC;
SystemVerilog;
design languages;
12.
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
机译:
保证带宽在芯片上的Nostrum网络中的时间差别不相交的网络中使用循环容器
作者:
Millberg M.
;
Nilsson E.
;
Thid R.
;
Jantsch A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
quality of service;
time division multiplexing;
hardware description languages;
high level synthesis;
system-on-chip;
network routing;
packet switching;
guaranteed bandwidth;
looped containers;
temporally disjoint networks;
nostrum network on-chip;
quality of service;
network on-chip architecture;
best effort traffic;
virtual circuits;
VC;
deflective routing policy;
time division multiplexing;
HDL implementation;
hardware description languages;
high level synthesis;
13.
Efficient modular testing of SoCs using dual-speed TAM architectures
机译:
使用双速TAM架构的高效模块化测试SOC
作者:
Sehgal A.
;
Chakrabarty K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
automatic test equipment;
integrated circuit design;
integrated circuit testing;
modular testing;
SoC;
dual-speed TAM architectures;
automatic test equipment;
port scalability;
test processor-per-pin architecture;
Tiger system;
tester channels;
resource limitations;
power rating;
scan frequency limits;
embedded cores;
optimization problem;
SOC-level TAM;
heuristic algorithm;
TAM optimization;
14.
Managing don't cares in Boolean satisfiability
机译:
管理不关心布尔可靠性
作者:
Safarpour S.
;
Veneris A.
;
Drechsler R.
;
Lee J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
Boolean functions;
computability;
don't cares;
Boolean satisfiability;
satisfiability solvers;
CAD VLSI;
circuit representation;
structural circuit characteristics;
search space;
decision making process;
15.
A new effective congestion model in floorplan design
机译:
平面图设计中的一种新的有效拥塞模型
作者:
Yi-Lin Hsieh
;
Tsai-Ming Hsieh
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
circuit layout;
network routing;
probability;
irregular grid congestion model;
floorplan design;
probabilistic analysis;
routing information;
fixed size grids;
16.
Formal refinement and model checking of an echo cancellation unit
机译:
回声消除单位的正式细化和模型检查
作者:
Krupp A.
;
Mueller W.
;
Oliver I.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
echo suppression;
formal verification;
specification languages;
real-time systems;
formal refinement;
model checking;
digital echo cancellation unit;
state based real time systems;
UML state diagrams;
unified modeling language;
formal-B language;
Atelier-B theorem;
abstract representation;
17.
Hierarchical adaptive dynamic power management
机译:
分层自适应动态电源管理
作者:
Zhiyuan Ren
;
Krogh B.H.
;
Marculescu R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
circuit optimisation;
Markov processes;
power consumption;
low-power electronics;
hierarchical adaptive dynamic power management;
DPM;
nonstationary service requests;
Markov-modulated stochastic process;
modulation state models;
stationary mode;
arrival process;
hierarchical architecture;
policy optimization;
Markov decision processes;
supervisory power manager;
mode-switching arrival dynamics;
power savings;
heuristic approaches;
low-power design;
18.
Arithmetic reasoning in DPLL-based SAT solving
机译:
基于DPLL的SAT求解的算术推理
作者:
Wedler M.
;
Stoffel D.
;
Kunz W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
digital arithmetic;
computability;
formal verification;
problem solving;
arithmetic reasoning;
DPLL-based SAT solving;
Davis Putnam Longman Loveland;
DPLL;
arithmetic bit level description;
arithmetic circuit parts;
RTL property checker;
formal verification;
19.
Digital background gain error correction in pipeline ADCs
机译:
数字背景在管道ADC中获得纠错
作者:
Gines A.J.
;
Peralias E.J.
;
Rueda A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue-digital conversion;
calibration;
gain measurement;
error correction;
digital background;
gain error correction;
pipeline ADC;
digital technique;
background calibration;
MDAC;
dynamic rate;
input-output characteristics;
digital noise signal;
analogue-to-digital converter;
on-line calibration;
20.
Impact of test point insertion on silicon area and timing during layout
机译:
测试点插入在布局期间硅面积和时序的影响
作者:
Vranken H.
;
Sapei F.S.
;
Wunderlich H.-J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
logic testing;
flip-flops;
circuit layout;
test point insertion;
silicon area;
circuits testability;
industrial circuits;
21.
Thermal and power integrity based power/ground networks optimization
机译:
基于热量和功率完整性的功率/地面网络优化
作者:
Ting-Yuan Wang
;
Jeng-Liang Tsai
;
Chung-Ping Chen C.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
power transmission reliability;
power supply quality;
optimisation;
electromigration;
thermal integrity;
power integrity;
power/ground network optimization;
VLSI designs;
very large scale integration design;
thermal effects;
thermal aware power delivery optimization algorithm;
thermal reliability;
electromigration;
9.5 year;
22.
A simulation-based power-aware architecture exploration of a multiprocessor system-on-chip design
机译:
基于模拟的电源感知架构探讨了多处理器系统片式设计
作者:
Menichelli F.
;
Olivieri M.
;
Benini L.
;
Donno M.
;
Bisdounis L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
multiprocessing systems;
system-on-chip;
ad hoc networks;
integrated circuit design;
simulation based power aware architecture;
multiprocessor system-on-chip design;
HIPERLAN/2 communication protocol;
ad-hoc C++ simulation environment;
power model integration;
CPU;
central processing unit;
DMA unit;
direct memory access;
software mapping;
23.
Interactive cosimulation with partial evaluation
机译:
与部分评估的互动性化妆
作者:
Schaumont P.
;
Verbauwhede I.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware-software codesign;
circuit simulation;
circuit optimisation;
integrated circuit design;
interactive cosimulation;
partial evaluation;
hardware-software cosimulation;
simulator compile-time;
abstraction levels;
interactive codesign environment;
AES encryption coprocessor;
Viterbi decoder;
instruction-set simulators;
SystemC-based cosimulation;
24.
A scalable implementation of a reconfigurable WCDMA RAKE receiver
机译:
可扩展的可重新配置WCDMA Rake接收器的实现
作者:
Quax M.
;
Huisken J.
;
van Meerbergen J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
code division multiple access;
mobile communication;
application specific integrated circuits;
radio receivers;
reconfigurable architectures;
RAKE receiver;
wideband code division multiple access;
mobile communication;
ASIC;
application specific integrated circuits;
reconfigurable processors;
programmable processing architectures;
programmable embedded computing;
25.
State-preserving vs. non-state-preserving leakage control in caches
机译:
缓存中的状态保留与非状态保留泄漏控制
作者:
Yingmin Li
;
Parikh D.
;
Yan Zhang
;
Sankaranarayanan K.
;
Stan M.
;
Skadron K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
cache storage;
memory architecture;
leakage currents;
electric current control;
state-preserving leakage control;
nonstate-preserving leakage control;
drowsy cache;
gated-V/sub ss/;
data caches;
HotLeakage;
subthreshold;
gate leakage;
parameter variation;
26.
Using a victim buffer in an application-specific memory hierarchy
机译:
在特定于应用程序的内存层次结构中使用受害者缓冲区
作者:
Chuanjun Zhang
;
Vahid F.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
application specific integrated circuits;
memory architecture;
cache storage;
buffer circuits;
victim buffer;
application-specific memory hierarchy;
embedded system design;
cache parameters;
line size;
PowerStone;
MediaBench benchmarks;
direct-mapped cache;
memory-access energy;
performance overhead;
core-based platform;
prefabricated platform;
27.
Improved symoblic simulation by dynamic funtional space partitioning symoblic read symbolic funtional read functional
机译:
通过动态功能空间分区改进符号模拟符号读符号 娱乐读功能
作者:
Tao Feng
;
Wang L.-C.
;
Kwang-Ting Cheng
;
Lin A.C.-C.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
logic partitioning;
circuit simulation;
binary decision diagrams;
symbol manipulation;
symbolic simulation;
dynamic functional space partitioning;
2-tuple list representation;
OBDD;
optimal partitioning points;
time complexity;
space complexity;
floating point adder;
memory management unit;
ordered binary decision diagram;
28.
A new optimized implementation of the SystemC engine using acyclic scheduling
机译:
使用无线环路调度的系统C引擎的新优化实现
作者:
Perez D.G.
;
Mouchard G.
;
Temam O.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
simulation languages;
digital simulation;
processor scheduling;
circuit optimisation;
system-on-chip;
embedded systems;
SystemC engine;
acyclic scheduling;
SoC;
embedded processors;
SystemC framework;
cycle-level simulation;
design space exploration;
software engineering;
dynamic scheduling;
static scheduling;
process wake-ups;
scheduling algorithm;
29.
Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip
机译:
保证带宽在芯片上的Nostrum网络中的时间差别不相交的网络中使用循环容器
作者:
Millberg M.
;
Nilsson E.
;
Thid R.
;
Jantsch A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
quality of service;
time division multiplexing;
hardware description languages;
high level synthesis;
system-on-chip;
network routing;
packet switching;
guaranteed bandwidth;
looped containers;
temporally disjoint networks;
nostrum network on-chip;
quality of service;
network on-chip architecture;
best effort traffic;
virtual circuits;
VC;
deflective routing policy;
time division multiplexing;
HDL implementation;
hardware description languages;
high level synthesis;
30.
Hybrid architectural dynamic thermal management
机译:
混合架构动态热管理
作者:
Skadron K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
microprocessor chips;
integrated circuit design;
thermal management (packaging);
low-power electronics;
hybrid architectural dynamic thermal management;
DTM;
power density;
operating temperatures;
heat dissipation;
processor-architecture techniques;
fetch gating;
dynamic voltage scaling;
DVS;
thermal stress;
instruction-level parallelism;
ILP;
31.
NeuroFPGA-implementing artificial neural networks on programmable logic devices
机译:
NeurofPGA-在可编程逻辑器件上实施人工神经网络
作者:
Ferrer D.
;
Gonzalez R.
;
Fleitas R.
;
Acle J.P.
;
Canetti R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
programmable logic devices;
multilayer perceptrons;
field programmable gate arrays;
network synthesis;
programmable logic devices;
multilayer perceptron neural network;
artificial neural networks;
FPGA;
field programmable gate arrays;
Matlab neural network toolbox;
circuit design;
32.
Dynamic power management using data buffers
机译:
使用数据缓冲区的动态电源管理
作者:
Le Cai
;
Yung-Hsiang Lu
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
buffer storage;
microprocessor chips;
circuit optimisation;
power consumption;
dynamic power management;
data buffers;
energy consumption;
optimal energy savings;
data arrival rates;
data departure rates;
electronic systems;
wireless network interface cards;
WNIC;
33.
Extremely low-power logic
机译:
极低功耗逻辑
作者:
Piguet C.
;
Gautier J.
;
Heer C.
;
OConnor I.
;
Schlichtmann U.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
logic design;
optical interconnections;
integrated circuit design;
integrated circuit interconnections;
nanoelectronics;
low-power electronics;
low-power logic;
reduced supply voltages;
logic blocks;
on-chip optical interconnect;
nanodevices;
34.
Aspects of formal and graphical design of a bus system
机译:
总线系统的正式和图形设计的方面
作者:
Seceleanu T.
;
Westerlund T.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system buses;
graphical user interfaces;
asynchronous circuits;
specification languages;
formal design;
graphical design;
bus system;
bus arbiter;
formal framework;
action systems;
UML profile notations;
hardware design decision;
graphical environment;
35.
Saving power by mapping finite-state machines into embedded memory blocks in FPGAs
机译:
通过将有限状态机器映射到FPGA中的嵌入式存储器块来节省电力
作者:
Tiwari A.
;
Tomko K.A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
finite state machines;
field programmable gate arrays;
power consumption;
clocks;
flip-flops;
embedded systems;
finite state machines mapping;
FPGA;
field programmable gate array;
on-chip synchronous embedded memory blocks;
flip-flops;
clock frequency;
power consumption;
36.
Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models
机译:
使用预编译的寄生感知符号性能模型快速,布局包容性模拟电路合成
作者:
Ranjan M.
;
Verhaegen W.
;
Agarwal A.
;
Sampath H.
;
Vemuri R.
;
Gielen G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue integrated circuits;
integrated circuit layout;
integrated circuit modelling;
network synthesis;
analog circuit synthesis;
parameterized layout generators;
symbolic performance models;
synthesis loop;
layout generation;
performance estimation;
precompiled SPM;
DDD-like structures;
element coefficient diagrams;
parasitic inclusion;
performance closure;
parasitic effects;
37.
Eliminating false positives in crosstalk noise analysis
机译:
消除串扰噪声分析中的误报
作者:
Ran Y.
;
Kondratyev A.
;
Watanabe Y.
;
Marek-Sadowska M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
interference suppression;
crosstalk;
timing;
Boolean functions;
delays;
noise elimination;
crosstalk noise analysis method;
circuit operation;
gate delays;
noise faults;
path delay;
Boolean logic;
signal transitions;
minmax delay model;
Boolean formulation;
38.
Heterogeneous co-simulation of networked embedded systems
机译:
网络嵌入式系统的异构共模
作者:
Fummi F.
;
Poncino M.
;
Martini S.
;
Ricciato F.
;
Perbellini G.
;
Turolla M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
embedded systems;
hardware-software codesign;
system-on-chip;
IP networks;
network routing;
transport protocols;
networked embedded systems;
hardware-software codesign;
systemC;
network simulator;
system on chip;
IP networks;
IPv4 routing;
39.
Extended subspace identification of improper linear systems
机译:
不正确的线性系统的扩展子空间识别
作者:
Vandersteen G.
;
Pintelon R.
;
Linten D.
;
Donnay S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
linear systems;
transfer functions;
state-space methods;
frequency-domain synthesis;
identification;
electric admittance;
extended subspace identification;
improper linear systems;
linear transfer functions;
electronic system simulation;
on-chip inductors modeling;
2-port measurements;
state-space models;
proper systems;
admittance matrix;
extended state-space model;
frequency-domain subspace identification;
commercial solutions;
coplanar waveguide;
40.
MATLAB/SIMULINK-based high-level synthesis of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators
机译:
基于MATLAB / SIMULINK的离散时间和连续时间/ SPL SIGMA // SPL DELTA /调制器的高级合成
作者:
Ruiz-Amaya J.
;
de la Rosa J.M.
;
Medeiro F.
;
Fernandez F.V.
;
del Rio R.
;
Perez-Verdu B.
;
Rodriguez-Vazquez A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
sigma-delta modulation;
high level synthesis;
circuit optimisation;
digital simulation;
discrete time systems;
continuous time systems;
/spl Sigma//spl Delta/ modulators;
automated high level synthesis;
time domain behavioural simulator;
statistical optimizer;
digital simulation;
41.
Implementation of a UMTS turbo-decoder on a dynamically reconfigurable platform
机译:
在动态可重新配置平台上实现UMTS Turbo-解码器
作者:
La Rosa A.
;
Passerone C.
;
Gregoretti F.
;
Lavagno L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
3G mobile communication;
turbo codes;
decoding;
reconfigurable architectures;
reduced instruction set computing;
field programmable gate arrays;
program processors;
software engineering;
UMTS turbo decoder;
universal mobile telecommunication system;
reconfigurable platforms;
embedded systems;
audio compression;
image compression;
channel coding;
channel encoding;
XiRisc reconfigurable processor;
reduced instruction set computing;
embedded software development;
field programmable gate arrays;
42.
Customisable EPIC processor: architecture and tools
机译:
可定制的史诗处理器:架构和工具
作者:
Chu W.W.S.
;
Dimond RG
;
Perrott S.
;
Seng S.P.
;
Luk W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
parallel processing;
pipeline processing;
optimising compilers;
program assemblers;
field programmable gate arrays;
customisable architecture;
explicitly parallel instruction computing processor;
compiler;
assembler;
Trimaran framework;
FPGA;
field programmable gate arrays;
ARM SA-110 processor;
41.8 MHz;
43.
Balanced excitation and its effect on the fortuitous detection of dynamic defects
机译:
平衡励磁及其对偶然检测动态缺陷的影响
作者:
Dworak J.
;
Cobb B.
;
Wingfield J.
;
Mercer M.R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
automatic test pattern generation;
fault diagnosis;
balanced excitation;
fortuitous detection;
dynamic defects;
automatic test pattern generation;
fault diagnosis;
44.
Early SEU fault injection in digital, analog and mixed signal circuits: a global flow
机译:
早期的SEU故障注入数字,模拟和混合信号电路:全球流动
作者:
Leveugle R.
;
Ammari A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue integrated circuits;
digital integrated circuits;
mixed analogue-digital integrated circuits;
fault simulation;
transient analysis;
integrated circuit testing;
integrated circuit reliability;
SEU fault injection;
digital circuits;
analog circuits;
mixed signal circuits;
global analysis flow;
high-level circuit model;
transient fault injection;
single event upsets;
45.
Low power analogue 90 degree phase shifter
机译:
低功率模拟90度移位器
作者:
Saul P.H.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
CMOS analogue integrated circuits;
phase shifters;
Hilbert transforms;
cellular radio;
reuseable circuit module;
analogue 90 degree phase shifter;
Hilbert transformer;
0.35 micron CMOS process;
sideband suppression;
statistical design technique;
current consumption;
SSB receivers;
communication architecture;
GSM;
DCS;
sonar;
global system for mobile communications;
digital cellular service;
single sideband receivers;
236 muA;
3.3 V;
46.
An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration
机译:
有效的片上网络接口,提供有保证的服务,共享 - 内存抽象和灵活的网络配置
作者:
Radulescu A.
;
Dielissen J.
;
Goossens K.
;
Rijpkema E.
;
Wielage P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
network interfaces;
shared memory systems;
protocols;
system-on-chip;
on-chip network interface;
shared memory abstraction;
network configuration;
transaction based protocol;
backward compatibility;
bus protocols;
0.143 mm;
0.13 micron;
500 MHz;
47.
Status of IEEE testability standards 1149.4, 1532 and 1149.6
机译:
IEEE可测试性标准1149.4,1532和1149.6
作者:
Bennetts B.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
IEEE standards;
boundary scan testing;
IEEE testability standards;
Institute of Electrical and Electronics Engineers;
multiboard testability;
boundary scan technology;
48.
Identification and modelling of nonlinear dynamic behaviour in analogue circuits
机译:
模拟电路中非线性动态行为的识别与建模
作者:
Xiaoling Huang
;
Mantooth H.A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
nonlinear dynamical systems;
analogue circuits;
differential equations;
modelling;
identification;
identification;
nonlinear dynamic behaviour;
analogue circuits;
model creation;
circuit dynamic behaviour;
automated modelling tool;
behavioural modelling tool;
Ascend;
netlist description;
differential algebraic equation;
DAE based behavioural models;
test results;
49.
Hybrid architectural dynamic thermal management
机译:
混合架构动态热管理
作者:
Skadron K.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
microprocessor chips;
integrated circuit design;
thermal management (packaging);
low-power electronics;
hybrid architectural dynamic thermal management;
DTM;
power density;
operating temperatures;
heat dissipation;
processor-architecture techniques;
fetch gating;
dynamic voltage scaling;
DVS;
thermal stress;
instruction-level parallelism;
ILP;
50.
Bandwidth-constrained mapping of cores onto NoC architectures
机译:
带宽约束核心在NoC架构上的映射
作者:
Murali S.
;
De Micheli G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
digital signal processing chips;
multimedia communication;
telecommunication network routing;
telecommunication links;
macros;
packet switching;
bandwidth constrained mapping;
monolithic systems;
processing cores;
communication links;
multimedia processing;
mesh based networks-on-chip architecture;
bandwidth constraints;
single path deterministic routing;
communication delay;
NMAP algorithm;
split traffic routing;
DSP design;
SystemC;
macros;
/spl times/pipes library;
video processing;
communication cost;
packet switching;
51.
A new optimized implementation of the SystemC engine using acyclic scheduling
机译:
使用无线环路调度的系统C引擎的新优化实现
作者:
Perez D.G.
;
Mouchard G.
;
Temam O.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
simulation languages;
digital simulation;
processor scheduling;
circuit optimisation;
system-on-chip;
embedded systems;
SystemC engine;
acyclic scheduling;
SoC;
embedded processors;
SystemC framework;
cycle-level simulation;
design space exploration;
software engineering;
dynamic scheduling;
static scheduling;
process wake-ups;
scheduling algorithm;
52.
Evaluation of a refinement-driven systemC/spl trade/-based design flow
机译:
评估改进驱动的SystemC / SPL贸易/基于设计流程
作者:
Schubert T.
;
Hanisch J.
;
Gerlach J.
;
Appell J-E
;
Nebel W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
high level languages;
specification languages;
refinement driven systemC/spl trade/ based design flow;
automotive digital hardware design;
high level executable specification;
refinement process;
gate level description;
VHDL based register transfer level design flow;
hardware description languages;
53.
Design of routing-constrained low power scan chains
机译:
路由约束低功率扫描链的设计
作者:
Bonhomme Y.
;
Girard P.
;
Guiller L.
;
Landrault C.
;
Pravossoudovitch S.
;
Virazel A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
low-power electronics;
boundary scan testing;
cluster tools;
circuit layout CAD;
routing-constrained low power scan chains;
scan-based architectures;
power consumption;
clustering;
reordering;
scan testing;
scan routing;
scan cells;
scan design constraints;
scan connections;
congestion problems;
54.
Performance modeling of analog integrated circuits using least-squares support vector machines
机译:
使用最小二乘支持向量机模拟集成电路性能建模
作者:
Kiely T.
;
Gielen G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
support vector machines;
least squares approximations;
analogue integrated circuits;
performance evaluation;
design of experiments;
reliability;
simulation;
regression analysis;
performance modelling;
analog integrated circuits;
least-squares support vec;
55.
Asynchronous design by conversion: converting synchronous circuits into asynchronous ones
机译:
转换的异步设计:将同步电路转换为异步
作者:
Branover A.
;
Kol R.
;
Ginosar R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
asynchronous circuits;
logic design;
combinational circuits;
asynchronous design;
synchronous circuits;
asynchronous circuits;
asynchronous system design;
conversion algorithm;
doubly latched asynchronous pipeline architecture;
power management;
logic design;
56.
Bandwidth-constrained mapping of cores onto NoC architectures
机译:
带宽约束核心在NoC架构上的映射
作者:
Murali S.
;
De Micheli G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
digital signal processing chips;
multimedia communication;
telecommunication network routing;
telecommunication links;
macros;
packet switching;
bandwidth constrained mapping;
monolithic systems;
processing cores;
communication links;
multimedia processing;
mesh based networks-on-chip architecture;
bandwidth constraints;
single path deterministic routing;
communication delay;
NMAP algorithm;
split traffic routing;
DSP design;
SystemC;
macros;
/spl times/pipes library;
video processing;
communication cost;
packet switching;
57.
Scan power minimization through stimulus and response transformations
机译:
通过刺激和响应变换扫描功率最小化
作者:
Sinanoglu O.
;
Orailoglu A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
boundary scan testing;
integrated circuit testing;
logic testing;
system-on-chip;
scan power minimization;
stimulus;
response transformations;
scan-based cores;
test power;
switching activity;
shift cycles;
SOC designers;
parallelism;
power thresholds;
SOC cores;
SOC test application time;
scan chain modification technique;
logic gates;
data transformations;
matrix band algebra;
58.
Synthesis of embedded systemC design: a case study of digital neural networks
机译:
嵌入式系统设计的合成 - 以数字神经网络为例
作者:
Lettnin D.
;
Braun A.
;
Bodgan M.
;
Gerlach J.
;
Rosenstiel W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
embedded systems;
system-on-chip;
hardware description languages;
multilayer perceptrons;
electrocardiography;
pattern recognition;
field programmable gate arrays;
high level synthesis;
embedded systemC design;
digital neural networks;
system on silicon design;
systemC specification language;
multilayer perceptron neural network;
electrocardiogram pattern recognition system;
behavioral integrated system synthesis;
preprocessing methodology;
hardware neural network design;
FPGA;
field programmable gate array;
high level systemC synthesis;
hardware description language;
59.
Modeling shared resource contention using a hybrid simulation/analytical approach
机译:
使用混合仿真/分析方法建模共享资源争用
作者:
Bobrek A.
;
Pieper J.J.
;
Nelson J.E.
;
Paul J.M.
;
Thomas D.E.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hybrid simulation;
modelling;
system-on-chip;
shared memory systems;
operating system kernels;
shared resource contention;
modeling;
hybrid simulation;
system-on-chip;
multiple heterogeneous processing unit;
data dependent shared resource;
piecewise evaluation;
multiprocessor applications;
Kernel operation;
60.
High-level system modeling and architecture exploration with SystemC on a network SoC: S3C2510 case study
机译:
网络SOC上系统的高级系统建模与架构探索:S3C2510案例研究
作者:
Hye-On Jang
;
Minsoo Kang
;
Myeong-jin Lee
;
Kwanyeob Chae
;
Kookpyo Lee
;
Kyuhyun Shim
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
high level synthesis;
integrated circuit modelling;
computer architecture;
high-level system modeling;
architecture exploration;
network SoC;
high-level design;
SystemC models;
Verilog RTL models;
on-chip test;
board performance simulation;
SystemC-based platform;
register transfer level;
61.
NeuroFPGA-implementing artificial neural networks on programmable logic devices
机译:
NeurofPGA-在可编程逻辑器件上实施人工神经网络
作者:
Ferrer D.
;
Gonzalez R.
;
Fleitas R.
;
Acle J.P.
;
Canetti R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
programmable logic devices;
multilayer perceptrons;
field programmable gate arrays;
network synthesis;
programmable logic devices;
multilayer perceptron neural network;
artificial neural networks;
FPGA;
field programmable gate arrays;
Matlab neural network toolbox;
circuit design;
62.
Intermittent scan chain fault diagnosis based on signal probability analysis
机译:
基于信号概率分析的间歇扫描链故障诊断
作者:
Yu Huang
;
Wu-Tung Cheng
;
Cheng-Ju Hsieh
;
Huan-Yung Tseng
;
Alou Huang
;
Yu-Ting Hung
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
fault diagnosis;
probability;
boundary scan testing;
multiple intermittent scan chain fault diagnosis;
signal probability analysis;
scan based designs;
industrial designs;
63.
Cost-performance trade-offs in networks on chip: a simulation-based approach
机译:
芯片网络中的成本性能权衡:基于模拟的方法
作者:
Pestana S.G.
;
Rijpkema E.
;
Radulescu A.
;
Goossens K.
;
Gangwal O.P.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
XML;
network interfaces;
network routing;
network topology;
circuit simulation;
cost performance trade offs;
networks-on-chip;
SoC;
systems-on-chip;
XML;
extensible markup languages;
network routing;
network topology;
network interface queue depth;
64.
How can system level design solve the interconnect technology scaling problem?
机译:
系统级设计如何解决互连技术缩放问题?
作者:
Catthoor F.
;
Cuomo A.
;
Martin G.
;
Groeneveld P.
;
Rudy L.
;
Maex K.
;
van de Steeg P.
;
Wilson R.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
integrated circuit design;
integrated circuit interconnections;
circuit layout CAD;
system level design;
interconnect technology scaling problem;
interconnect delay;
Moore law;
interconnect semiconductor technology;
65.
Low cost analogue testing of RF signal paths
机译:
RF信号路径的低成本模拟测试
作者:
Negreiros M.
;
Carro L.
;
Susin A.A.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
analogue integrated circuits;
integrated circuit testing;
built-in self test;
system-on-chip;
low cost analogue testing;
RF signal paths;
BIST implementation;
SoC environment;
one-bit digitizer;
processor reuse;
memory resources;
analogue area overhead;
66.
SoftContract: an assertion-based software development process that enables design-by-contract
机译:
SoftContract:基于断言的软件开发过程,可启用签名
作者:
Brunel J.-Y.
;
Di Natale M.
;
Ferrari A.
;
Giusto P.
;
Lavagno L.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
hardware description languages;
distributed object management;
software development management;
temporal logic;
SoftContract;
assertion-based software development process;
design-by-contract;
model-based design flow;
distributed embedded software development;
linear temporal logic;
assertion-based verification;
automated generation;
property-checking code;
multiple target languages;
67.
Mapping multi-million gate SoCs on FPGAs: industrial methodology and experience
机译:
在FPGA上映射数百万门SOC:工业方法论和体验
作者:
Krupnova H.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
software prototyping;
silicon;
elemental semiconductors;
field programmable gate arrays;
circuit complexity;
integrated circuits;
SoC software development;
system-on-chip;
hardware platform;
silicon;
multiFPGA prototype;
field programmable gate arrays;
circuit complexity;
state of the art mapping;
prototyping tools;
FPGA platform;
microelectronics SoC;
ASIC gates;
application specific integrated circuit;
Si;
68.
A fast word-level statistical estimator of intra-bus crosstalk
机译:
公交车内串扰的快速词级统计估算器
作者:
Gupta S.
;
Katkoori S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
sampling methods;
probability;
computational complexity;
crosstalk;
system buses;
estimation theory;
correlation theory;
table lookup;
word level statistical estimator;
intra bus crosstalk;
word level statistics;
standard deviation;
temporal correlation;
bitlevel crosstalk probability;
system bus;
sampling;
stream based estimator;
statistical nonenumerative technique;
linear time complexity;
exponential time complexity;
lookup table;
69.
Qualification and integration of complex I/O in SoC design flows
机译:
SoC设计流动中复杂I / O的资格与集成
作者:
Abraham J.
;
Rao G.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
system-on-chip;
nanotechnology;
complex I/O design;
complex input/output design;
SoC design flows;
system on chip design flows;
intellectual property integration;
digital design;
nanotechnology;
70.
A fast word-level statistical estimator of intra-bus crosstalk
机译:
公交车内串扰的快速词级统计估算器
作者:
Gupta S.
;
Katkoori S.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
sampling methods;
probability;
computational complexity;
crosstalk;
system buses;
estimation theory;
correlation theory;
table lookup;
word level statistical estimator;
intra bus crosstalk;
word level statistics;
standard deviation;
temporal correlation;
bitlevel crosstalk probability;
system bus;
sampling;
stream based estimator;
statistical nonenumerative technique;
linear time complexity;
exponential time complexity;
lookup table;
71.
Demonstration of a SiGe RF LNA design using IBM design kits in 0.18 /spl mu/m SiGe BiCMOS technology
机译:
使用IBM设计试剂盒在0.18 / SPL MU / M SIGE BICMOS技术中使用IBM设计试剂盒演示SIGE RF LNA设计
作者:
Yiming Chen
;
Xiaojuen Yuan
;
Scagnelli D.
;
Mecke J.
;
Gross J.
;
Harame D.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
UHF amplifiers;
radiofrequency integrated circuits;
integrated circuit design;
BiCMOS integrated circuits;
Ge-Si alloys;
semiconductor materials;
0.18 /spl mu/m SiGe BiCMOS technology;
SiGe RF LNA design;
radiofrequency low noise amplifier;
IBM design kits;
cadence design flow;
LNA chip;
RFIC design;
0.18 micron;
1.5 to 2.0 GHz;
GeSi;
72.
Customisable EPIC processor: architecture and tools
机译:
可定制的史诗处理器:架构和工具
作者:
Chu W.W.S.
;
Dimond RG
;
Perrott S.
;
Seng S.P.
;
Luk W.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
parallel processing;
pipeline processing;
optimising compilers;
program assemblers;
field programmable gate arrays;
customisable architecture;
explicitly parallel instruction computing processor;
compiler;
assembler;
Trimaran framework;
FPGA;
field programmable gate arrays;
ARM SA-110 processor;
41.8 MHz;
73.
Managing don't cares in Boolean satisfiability
机译:
管理不关心布尔可靠性
作者:
Safarpour S.
;
Veneris A.
;
Drechsler R.
;
Lee J.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
Boolean functions;
computability;
don't cares;
Boolean satisfiability;
satisfiability solvers;
CAD VLSI;
circuit representation;
structural circuit characteristics;
search space;
decision making process;
74.
Dynamic power management using data buffers
机译:
使用数据缓冲区的动态电源管理
作者:
Le Cai
;
Yung-Hsiang Lu
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
buffer storage;
microprocessor chips;
circuit optimisation;
power consumption;
dynamic power management;
data buffers;
energy consumption;
optimal energy savings;
data arrival rates;
data departure rates;
electronic systems;
wireless network interface cards;
WNIC;
75.
Impact of data transformations on memory bank locality
机译:
数据转换对内存银行局部的影响
作者:
Kandemir M.
会议名称:
《Automation and Test in Europe Conference and Exhibition》
|
2004年
关键词:
memory architecture;
integrated circuit design;
circuit optimisation;
low-power electronics;
data transformations;
memory bank locality;
clock frequency;
clock deliverable performance;
memory energy consumption;
array-intensive applications;
cache locality;
banked memory architecture;
memory space;
bank access pattern;
data layout transformation strategy;
array layouts;
loop iterations;
low-power mode;
memory banking;
operating modes;
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