SystemC and SystemVerilog: Where do they fit? Where are they going?

摘要

There is tremendous interest in design languages these days - and more particularly, SystemC and SystemVerilog. Sometimes the truth about design languages can be obscured by marketing and the press. This panel is meant to deepen the technical understanding of the DATE audience on the issue of design languages. It contains five technical experts - an academic expert in design languages and SystemC and SystemVerilog in particular; a language expert for each of SystemC and SystemVerilog; and a user expert for these two languages. The language experts have been heavily involved in the specification and evolution of their respective languages. The user experts have been heavily involved in developing use methodologies for these languages within their own design communities, and in applying them to real design problems. The panellists will consider the questions: 1) what are the key capabilities of these languages and what do they offer to users?; 2) which design problems are they best used for? what is their scope?; 3) how has application of these languages to real design problems improved the productivity of designers and the quality of the design results?; and 4) where should the languages develop further capabilities?.