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Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France
Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France
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1.
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors
机译:
针对软错误的选择性硬化的逻辑掩盖效应的可扩展计算
作者:
Polian
;
I.
;
Reddy
;
S.M.
;
Becker
;
B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
error statistics;
fault diagnosis;
integrated circuit testing;
radiation hardening (electronics);
error probability reduction;
fault detection probabilities;
industrial multiple-million-gates circuits;
logical masking effects;
maximal soft error rate reduction;
s;
2.
A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory
机译:
具有卤化银全息照相存储器的动态光学可重构门阵列
作者:
Seto
;
D.
;
Watanabe
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
holographic optical elements;
logic arrays;
photodiodes;
dynamic optically reconfigurable gate array;
junction capacitance;
liquid crystal holographic memory;
photodiodes;
silver-halide holographic memory;
Field Programmable Gate Arrays;
Optically Reconfigurable;
3.
Energy Recovery from High-Frequency Clocks Using DC-DC Converters
机译:
使用DC-DC转换器从高频时钟中回收能量
作者:
Alimadadi
;
M.
;
Sheikhaei
;
S.
;
Lemieux
;
G.
;
Mirabbasi
;
S.
;
Dunford
;
W.
;
Palmer
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
DC-DC power convertors;
clocks;
digital integrated circuits;
driver circuits;
clock duty cycle;
energy recovery;
high frequency clocks;
large digital chips;
multi GHz clock;
on-chip DC-DC converters;
single-edge-triggered flops;
tapered buffer chain;
dc-dc converter;
4.
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme
机译:
结合归约方案的放置后串扰估计的有效方法
作者:
Mehdizadeh
;
A.
;
Zamani
;
M.S.
;
Shafiei
;
H.
会议名称:
《》
关键词:
crosstalk;
integrated circuit noise;
network routing;
probability;
crosstalk estimation;
crosstalk reduction scheme;
failing noisy nets;
global routing;
intra-grid wirelength;
probabilistic method;
wirelength estimations;
Coupling Capacitance;
Crosstalk Noise;
Physic;
5.
A CMOS Multi-sensor System for 3D Orientation Determination
机译:
用于3D方向确定的CMOS多传感器系统
作者:
Alandry
;
B.
;
Dumas
;
N.
;
Latorre
;
L.
;
Mailly
;
F.
;
Nouet
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
accelerometers;
heat transfer;
microsensors;
monolithic integrated circuits;
piezoresistive devices;
3D orientation determination;
CMOS multisensor system;
Euler angles;
electromechanical compass;
front side bulk micromachining;
gyroscopes;
6.
Efficient High-Level Power Estimation for Multi-standard Wireless Systems
机译:
多标准无线系统的高效高级功率估计
作者:
Ahmadinia
;
A.
;
Ahmad
;
B.
;
Arslan
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
WiMax;
autoregressive moving average processes;
AMBA bus;
ARM processor;
SystemC;
Viterbi;
WiMAX receiver;
high-level power estimation;
multi-standard wireless systems;
reconfigurable FFT;
state based power modelling;
transaction level modelling;
7.
Modeling and Optimization of Switching Power Dissipation in Static CMOS Circuits
机译:
静态CMOS电路中开关功率耗散的建模与优化
作者:
Kabbani
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
invertors;
low-power electronics;
switching convertors;
BSIM3v3 model;
Spectre simulations;
average power saving;
logical path switching power;
power-delay products;
static CMOS circuits;
switching power dissipation;
unit standard inverter;
8.
Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture
机译:
自我动态可重配置架构的核心分配和重定位管理
作者:
Morandi
;
M.
;
Novati
;
M.
;
Santambrogio
;
M.D.
;
Sciuto
;
D.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
field programmable gate arrays;
reconfigurable architectures;
1D paradigm;
2D paradigm;
core allocation management;
core relocation management;
field programmable gate array;
runtime bitstream relocation;
self dynamically reconfigurable architecture;
validation p;
9.
Integrated Power-Gating and State Assignment for Low Power FSM Synthesis
机译:
低功耗FSM综合的集成电源门控和状态分配
作者:
Pradhan
;
S.N.
;
Kumar
;
M.T.
;
Chattopadhyay
;
S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
VLSI;
finite state machines;
genetic algorithms;
network synthesis;
dynamic power;
finite state machine decomposition;
genetic algorithmic approach;
logic block;
low power FSM synthesis;
power-gating;
standby leakage power;
state assignment;
state encoding strategy;
10.
Standard Cell Like Via-Configurable Logic Block for Structured ASICs
机译:
标准单元式结构化ASIC的可配置逻辑块
作者:
Mei-Chen Li
;
Hui-Hsiang Tung
;
Chien-Chung Lai
;
Rung-Bin Lin
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
application specific integrated circuits;
integrated logic circuits;
logic design;
cell library;
size 0.18 micron;
structured ASIC;
via-configurable logic block;
Programmable logic;
Regular fabric;
Standard cell;
Structured ASIC;
VLSI;
11.
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs
机译:
GePaRD-用于部分可重配置设计的高级生成流程
作者:
Boden
;
M.
;
Fiebig
;
T.
;
Reiband
;
M.
;
Reichel
;
P.
;
Rulke
;
S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
field programmable gate arrays;
high level synthesis;
logic design;
GePaRD;
high-level generation flow;
high-level synthesis;
partially reconfigurable FPGA;
partially reconfigurable designs;
self-adaptive systems;
temporal modularization;
temporal placement;
tempor;
12.
Flow Maximization for NoC Routing Algorithms
机译:
NoC路由算法的流量最大化
作者:
Ying-Cherng Lan
;
Chen
;
M.C.
;
Su
;
A.P.
;
Yu-Hen Hu
;
Sao-Jie Chen
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
network routing;
network-on-chip;
NoC routing algorithms;
decision flow;
flow maximization;
minimal adaptive routing scheme;
network-on-chip;
packet injection rates;
Adaptive Routing;
Congestion Control;
Network-on-Chip;
13.
Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip
机译:
片上虫洞交换网状网络的无死锁组播路由算法
作者:
Carara
;
E.A.
;
Moraes
;
F.G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
cache storage;
message passing;
multiprocessor interconnection networks;
network routing;
network-on-chip;
packet switching;
parallel algorithms;
cache coherence protocol;
circuit switching;
deadlock-free multicast routing algorithm;
distributed system;
dual-path m;
14.
Application of Bottom-Up Methodology to RTW VCO
机译:
自下而上的方法在RTW VCO中的应用
作者:
Ben Abdeljelil
;
F.
;
Nicolle
;
B.
;
Tatinian
;
W.
;
Carpineto
;
L.
;
Oudinot
;
J.
;
Jacquemod
;
G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
SPICE;
phase noise;
switched capacitor networks;
voltage-controlled oscillators;
EDA tools interoperability;
RTW VCO;
SPICE simulations;
block-level model;
bottom-up methodology;
bottom-up verification;
electromagnetic simulations;
frequency 14.35 GHz;
hierarchical;
15.
Low Standby Power and Robust FinFET Based SRAM Design
机译:
低待机功耗和稳健的基于FinFET的SRAM设计
作者:
Ebrahimi
;
B.
;
Zeinolabedinzadeh
;
S.
;
Afzali-Kusha
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
MOSFET;
SRAM chips;
integrated circuit design;
invertors;
leakage currents;
low-power electronics;
FinFET;
HSPICE simulation;
SRAM design;
cross-coupled inverter;
leakage power reduction;
low standby power consumption;
static noise margin;
FinFET;
Low-Power Memory;
SRA;
16.
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection
机译:
具有内置错误检测功能的VLSI互连中延迟和能量最小化的新编码方案
作者:
Avinash
;
L.
;
Krishna
;
M.K.
;
Srinivas
;
M.B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
VLSI;
crosstalk;
error detection;
integrated circuit interconnections;
microprocessor chips;
VLSI interconnects;
built-in error detection;
crosstalk noise;
deep sub-micron technology;
delay minimization;
energy minimization;
error detection requirement;
logic faults;
17.
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction
机译:
一种新的时钟网格缓冲区大小调整方法,可减少偏斜和功耗
作者:
Wilke
;
G.
;
Reis
;
R.
会议名称:
《》
关键词:
buffer storage;
clocks;
low-power electronics;
microprocessor chips;
clock mesh buffer sizing methodology;
mesh buffer propagation delays;
power reduction;
skew reduction;
Buffer sizing;
Clock;
Clock distribution;
Clock mesh;
18.
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects
机译:
将UML交互和面向角色的仿真应用于片上网络互连的设计空间探索
作者:
Indrusiak
;
L.S.
;
Ost
;
L.
;
Moller
;
L.
;
Moraes
;
F.
;
Glesner
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Unified Modeling Language;
integrated circuit interconnections;
logic CAD;
network-on-chip;
observability;
program debugging;
timing;
UML interactions;
actor-oriented simulation;
cycle-accurate RTL model;
debugging;
design space exploration;
network-on-chip intercon;
19.
Finding the Best Compromise in Compiling Compound Loops to Verilog
机译:
在将复合循环编译到Verilog中找到最佳折中方案
作者:
Ben-Asher
;
Y.
;
Shochat
;
E.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
hardware description languages;
integer programming;
linear programming;
Verilog;
high-level synthesis systems;
integer linear programming techniques;
list scheduling;
memory port;
optimized hardware configuration;
FPGA;
Synthesis;
Verilog;
loops;
nested;
20.
An Auto-adaptation Method for Dynamically Reconfigurable System-on-Chip
机译:
动态可重构片上系统的自适应方法
作者:
Xun Zhang
;
Rabah
;
H.
;
Weber
;
S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
data compression;
field programmable gate arrays;
image coding;
logic design;
reconfigurable architectures;
system-on-chip;
FPGA;
JPEG2000 application;
auto-adaptation method;
decompression algorithm;
dynamic frequency scaling;
dynamic reconfiguration;
partial recon;
21.
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines
机译:
多编解码器视频处理引擎中可变长度代码的编码和解码的通用设计
作者:
Prasad Arava
;
V.K.
;
Manhwee Jo
;
HyoukJoong Lee
;
Kiyoung Choi
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
data compression;
decoding;
encoding;
multimedia communication;
variable length codes;
video coding;
decoding;
encoding;
integrated multicodec engine;
lossless data compression;
mobile convergence;
multicodec video processing engines;
multimedia communication;
multip;
22.
Performance Improvement of Physical Retiming with Shortcut Insertion
机译:
通过快捷插入提高物理重定时的性能
作者:
Dokhanchi
;
A.
;
Rezvani
;
M.
;
Jahanian
;
A.
;
Zamani
;
M.S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
delay circuits;
iterative methods;
performance evaluation;
sequential circuits;
timing circuits;
Shannon decomposition;
circuit performance improvement;
critical cycle delay;
maximum cycle ratio;
physical retiming;
sequential circuits;
Maximum cycle ratio;
Shannon d;
23.
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs
机译:
利用外部JTAG接口进行Spartan 3 FPGA的内部控制配置回读和自重配置
作者:
Paulsson
;
K.
;
Viereck
;
U.
;
Hubner
;
M.
;
Becker
;
J.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit feedback;
field programmable gate arrays;
JCAP;
Spartan 3 FPGA;
Virtex 2/4;
Xilinx Spartan 3;
external JTAG interface;
field programmable gate arrays;
internally controlled configuration readback;
parallel computations;
partial hardware reconfiguration;
Low;
24.
An Efficient Area-Delay Product Design for MixColumns/InvMixColumns in AES
机译:
AES中MixColumns / InvMixColumns的高效面积延迟产品设计
作者:
Chung-Yi Li
;
Chih-Feng Chien
;
Jin-Hua Hong
;
Tsin-Yuan Chang
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
cryptography;
AT2;
TSMC CMOS technology;
XOR gates delay;
advanced encryption standard hardware;
area-delay product design;
critical delay;
decomposition method;
direct mapping S-boxes;
integrated InvMixColumns circuit;
integrated MixColum;
25.
Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis
机译:
同时调度,分配,绑定,重新排序和编码,以在高级综合期间最小化串扰模式
作者:
Sankaran
;
H.
;
Katkoori
;
S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
crosstalk;
high level synthesis;
scheduling;
simulated annealing;
DSP;
chip signal crosstalk;
crosstalk pattern minimization;
data transfer invert encoding;
latency constraints;
simulated annealing;
simultaneous scheduling;
Bus based designs;
Crosstalk;
HLS;
Re-orderi;
26.
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects
机译:
eSRAM虚拟位线驱动器的统计大小,用于在存在可变性方面提高读取余量
作者:
Min
;
M.Y.S.
;
Maurine
;
P.
;
Bastian
;
M.
;
Robert
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
SRAM chips;
driver circuits;
statistical analysis;
timing circuits;
SRAM design;
design process;
eSRAM dummy bitline driver;
operating voltage conditions;
read timing margin;
statistical design technique;
statistical sizing;
Dummy Bitline Driver;
Read Timing Margin;
27.
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier
机译:
在数字乘法器中建立和保持由过程变化引起的时序违规
作者:
Rebaud
;
B.
;
Belleville
;
M.
;
Bernard
;
C.
;
Wu
;
Z.
;
Robert
;
M.
;
Maurine
;
P.
;
Azemard
;
N.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Monte Carlo methods;
circuit CAD;
digital circuits;
multiplying circuits;
CAD tools;
Monte Carlo analysis;
RTL MAC multiplier-accumulator physical synthesis;
Statistical Static Timing Analysis method;
combinatory cells;
digital circuits;
digital multiplier;
flip-fl;
28.
Characterisation of FPGA Clock Variability
机译:
FPGA时钟可变性的表征
作者:
Sedcole
;
P.
;
Wong
;
J.S.
;
Cheung
;
P.Y.K.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
clocks;
delay-differential systems;
field programmable gate arrays;
integrated circuit design;
logic design;
FPGA;
clock skew;
clock variability;
differential delay measurement circuit;
integrated circuits;
size 65 nm;
BIST;
FPGA;
at-speed test;
clock skew;
process var;
29.
A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing
机译:
变量感知缓冲区插入和驱动程序大小确定的模糊方法
作者:
Mahalingam
;
V.
;
Ranganathan
;
N.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
buffer circuits;
driver circuits;
fuzzy set theory;
optimisation;
ITC''99 benchmarks;
circuit reliability;
deterministic optimizations;
driver sizing;
fuzzy approach;
fuzzy numbers;
fuzzy optimization technique;
fuzzy piece-wise linear program;
variation aware buffe;
30.
A Novel Multiple Core Co-processor Architecture for Efficient Server-Based Public Key Cryptographic Applications
机译:
一种新颖的多核协处理器体系结构,用于基于服务器的高效公钥加密应用
作者:
Laue
;
R.
;
Molter
;
H.G.
;
Rieder
;
F.
;
Huss
;
S.A.
;
Saxena
;
K.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
coprocessors;
hardware-software codesign;
parallel architectures;
public key cryptography;
system-on-chip;
HW/SW co-design;
HW/SW codesign;
SoC;
multiple core coprocessor architecture;
public key cryptographic;
server applications;
system-on-chip;
multi-core;
paralle;
31.
System Level Design Space Exploration for Multiprocessor System on Chip
机译:
多处理器片上系统的系统级设计空间探索
作者:
Maalej
;
I.
;
Gogniat
;
G.
;
Philippe
;
J.L.
;
Abid
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
logic design;
multiprocessing systems;
system-on-chip;
multiprocessor system on chip;
system level design space exploration;
32.
A Neural Stimulator Output Stage for Dodecapolar Electrodes
机译:
十二极电极的神经刺激器输出级
作者:
Soulier
;
F.
;
Lerat
;
J.-B.
;
Gouyet
;
L.
;
Bernard
;
S.
;
Cathebras
;
G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
application specific integrated circuits;
bioelectric phenomena;
biomedical electrodes;
neuromuscular stimulation;
ASIC;
dodecapolar electrodes;
functional electrical stimulation;
nervous system dysfunctions;
neural stimulator output stage;
Functional electro-sti;
33.
Benchmarking Domain Specific Processors: A Case Study of Evaluating a Smart Card Processor Design
机译:
对特定于域的处理器进行基准测试:评估智能卡处理器设计的案例研究
作者:
Zhonglei Wang
;
Wild
;
T.
;
Ruping
;
S.
;
Lippmann
;
B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
benchmark testing;
integrated circuit design;
microprocessor chips;
performance evaluation;
smart cards;
Java application;
benchmarking;
domain specific processors;
embedded system;
general-purpose computers;
performance analysis;
smart card processor design;
Benchm;
34.
Arithmetic Data Path Optimization Using Borrow-Save Representation
机译:
使用借位保存表示的算术数据路径优化
作者:
Belloeil
;
S.
;
Chotin-Avot
;
R.
;
Mehrez
;
H.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit CAD;
circuit optimisation;
discrete cosine transforms;
integrated circuit design;
redundant number systems;
adders;
arithmetic data path optimization;
borrow-save representation;
discrete cosine transform;
distance computation unit;
high computational digi;
35.
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era
机译:
自适应可靠芯片-纳米时代的可重构计算
作者:
Becker
;
J.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
embedded systems;
nanoelectronics;
reconfigurable architectures;
system-on-chip;
adaptive reliable chips;
embedded electronic systems;
multipurpose adaptivity;
reconfigurable computing;
reliability features;
silicon technologies;
systems-on-chip;
36.
Emerging Concepts in Non-volatile Memory Technologies - Era of Resistance Switching Memories
机译:
非易失性存储技术中的新兴概念-电阻切换存储器时代
作者:
Muller
;
C.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
embedded systems;
random-access storage;
reconfigurable architectures;
Moore''s goals;
embedded electronic systems;
multipurpose adaptivity;
nonvolatile memory technologies;
on-demand chip adaptivity;
real-time hardware reconfiguration;
reconfigurable computing;
r;
37.
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions
机译:
Shared-PPRM:布尔可逆函数的内存有效表示
作者:
Sanaee
;
Y.
;
Saeedi
;
M.
;
Zamani
;
M.S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Boolean functions;
data structures;
storage management;
Boolean reversible functions;
list-based data structures;
memory location;
memory usage;
memory-efficient representation;
Positive Polarity Reed-Muller Expansion;
Reversible circuits;
data structure;
38.
Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture
机译:
事务级别的SystemC中的电源建模,应用于DVFS架构
作者:
Lebreton
;
H.
;
Vivet
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit simulation;
low-power electronics;
network-on-chip;
power consumption;
DVFS architecture;
SoC;
SystemC;
TLM platform;
advanced power management strategies;
clock gating;
frequency scaling;
hardware level;
mobile systems;
network-on-chip;
power consumption;
powe;
39.
NoC Power Estimation at the RTL Abstraction Level
机译:
RTL抽象级别的NoC功率估算
作者:
Guindani
;
G.
;
Reinbrecht
;
C.
;
Raupp
;
T.
;
Calazans
;
N.
;
Moraes
;
F.G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
integrated circuit design;
network-on-chip;
NoC power estimation;
RTL abstraction level;
buffer reception rates;
industrial power estimation tools;
integrated circuits;
mobile electronic devices;
multicast service;
traffic scenario;
NoC;
multicast;
power estimation;
40.
An Efficient Motion Adaptive De-interlacing and Its VLSI Architecture Design
机译:
高效运动自适应去隔行及其VLSI架构设计
作者:
Hongbin Sun
;
Nanning Zheng
;
Chenyang Ge
;
Dong Wang
;
Pengju Ren
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Gaussian processes;
VLSI;
digital television;
filtering theory;
high definition television;
image motion analysis;
image reconstruction;
image texture;
integrated circuit design;
logic design;
Gaussian filtering;
HDTV application;
SDTV application;
VLSI architecture;
41.
Efficient Realization of Strongly Indicating Function Blocks
机译:
强指示功能块的有效实现
作者:
Balasubramanian
;
P.
;
Edwards
;
D.A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
logic circuits;
logic design;
digital circuit functionality;
dual-rail encoding;
four-phase handshaking;
gatelevel realization;
indicating function blocks;
quasidelay insensitivity;
42.
Virtual Point-to-Point Links in Packet-Switched NoCs
机译:
分组交换NoC中的虚拟点对点链接
作者:
Modarressi
;
M.
;
Sarbazi-Azad
;
H.
;
Tavakkol
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
graph theory;
integrated circuit design;
logic design;
low-power electronics;
network routing;
network-on-chip;
packet switching;
network-on-chip;
packet-switched NoC design;
power consumption;
router architecture;
task-graph mapping;
virtual point-to-point link;
App;
43.
Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip
机译:
片上系统电源门控方案中的地面反弹噪声控制
作者:
Chowdhury
;
M.H.
;
Gjanci
;
J.
;
Khaled
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit noise;
leakage currents;
system-on-chip;
ground bounce noise;
leakage currents;
peak current;
power distribution network;
power gating scheme;
power gating structures;
power mode transition;
system-on-a-chip;
voltage glitches;
Power gating;
ground bounce;
leak;
44.
A Web Server Based Edge Detector Implementation in FPGA
机译:
FPGA中基于Web服务器的边缘检测器实现
作者:
Shukla
;
S.
;
Bergmann
;
N.W.
;
Becker
;
J.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Internet;
client-server systems;
edge detection;
field programmable gate arrays;
file servers;
FPGA;
QUKU;
Web server-client implementation;
coarse grained dynamically reconfigurable PE array;
image edge detection;
microblaze soft-processor core;
remote image proce;
45.
Determining the Optimal Number of Islands in Power Islands Synthesis
机译:
确定功率岛综合中的最佳岛数
作者:
Dal
;
D.
;
Mansouri
;
N.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
VLSI;
distributed power generation;
high level synthesis;
digital VLSI design;
high level synthesis;
portable electronic devices;
power islands synthesis;
spurious switching activity;
threshold values;
Clique Partitioning;
Digital VLSI;
Dynamic Power;
High Level Syn;
46.
Cache Power Reduction in Presence of Within-Die Delay Variation Using Spare Ways
机译:
使用备用方法在存在模内延迟变化的情况下降低缓存功率
作者:
Goudarzi
;
M.
;
Matsumura
;
T.
;
Ishihara
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
SPICE;
cache storage;
leakage currents;
SPICE;
cache capacity;
cache power reduction;
cache transistors;
gate-level simulation;
gate-oxide thickness;
spare ways;
technology scaling;
threshold voltage;
timing yield;
within-die delay variation;
Cache;
Delay variation;
Lea;
47.
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability
机译:
使用更高级别的抽象通过布尔可满足性解决优化问题
作者:
Wille
;
R.
;
Grosse
;
D.
;
Soeken
;
M.
;
Drechsler
;
R.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Boolean algebra;
computability;
optimisation;
Boolean satisfiability;
abstraction;
bit-vector logic;
compact encoding;
decision problem;
graph coloring;
optimization problem;
reversible logic;
Bit-vector Logic;
Boolean Satisfiability;
Optimization Problems;
SMT;
Word L;
48.
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis
机译:
高级综合中设计空间探索的多目标遗传算法
作者:
Ferrandi
;
F.
;
Lanzi
;
P.L.
;
Loiacono
;
D.
;
Pilato
;
C.
;
Sciuto
;
D.
会议名称:
《》
关键词:
computational complexity;
genetic algorithms;
hardware description languages;
NP-complete;
arithmetic logic units;
design space exploration;
evolutionary algorithms;
high-level synthesis;
multi-modal functional units;
multi-objective genetic algorithm;
Design Spac;
49.
Fast Hardware Upper-Bound Power Estimation for a Novel FPGA-Based HW/SW Partitioning Scheme
机译:
基于FPGA的新型硬件/软件分配方案的快速硬件上限功率估计
作者:
Abdelhalim
;
M.B.
;
Habib
;
S.E.-D.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
electronic engineering computing;
field programmable gate arrays;
hardware-software codesign;
FPGA;
HW-SW partitioning scheme;
upper-bound power consumption estimation tool;
HW/SW Partitioning;
Power consumption Estimation;
50.
FSMD Partitioning for Low Power Using ILP
机译:
使用ILP进行FSMD分区以实现低功耗
作者:
Agarwal
;
N.
;
Dimopoulos
;
N.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
finite state machines;
integer programming;
linear programming;
low-power electronics;
FSMD partitioning;
ILP;
finite state machine with datapath;
integer linear programming;
power gating;
power savings;
FSMD;
ILP;
controller;
integer linear programming;
optimization;
51.
Smart-NICs: Power Proxying for Reduced Power Consumption in Network Edge Devices
机译:
智能网卡:电源代理以减少网络边缘设备的功耗
作者:
Sabhanatarajan
;
K.
;
Gordon-Ross
;
A.
;
Oden
;
M.
;
Navada
;
M.
;
George
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Internet;
internetworking;
network interfaces;
Internet;
Smart-NIC;
hardware-based packet classification;
network connectivity;
network edge devices;
network interface card;
network protocols;
packet-handling functions;
power proxying;
reduced power consumption;
52.
Defect Tolerance Inspired by Artificial Evolution
机译:
人工进化启发的缺陷容忍度
作者:
Djupdal
;
A.
;
Haddow
;
P.C.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
evolutionary computation;
fault tolerance;
integrated circuit reliability;
integrated circuit testing;
evolutionary algorithm;
gate-drain shorted transistor;
gate-source shorted transistor;
integrated circuit defect tolerance;
semiconductor feature size;
single s;
53.
Adaptive Neuron Activation Function with FGMOS Based Operational Transconductance Amplifier
机译:
基于FGMOS的运算跨导放大器的自适应神经元激活功能
作者:
Babu
;
V.S.
;
Rose
;
K.A.A.
;
Baiju
;
M.R.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
MOSFET;
neural nets;
operational amplifiers;
FGMOS based operational transconductance amplifier;
FGMOS transistors;
adaptive neuron activation function;
analog signal processing;
multiple input floating gate MOS transistor;
neural network;
operational transconduc;
54.
FPGA-Based Circuit Model Emulation of Quantum Algorithms
机译:
基于FPGA的量子算法电路模型仿真
作者:
Aminian
;
M.
;
Saeedi
;
M.
;
Zamani
;
M.S.
;
Sedighi
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
field programmable gate arrays;
quantum computing;
FPGA-based circuit model emulation;
quantum algorithms;
quantum bits;
quantum computers;
Hardware Emulation;
Quantum Circuits;
Quantum Computing;
55.
Cohesive Coverage Management for Simulation and Formal Property Verification
机译:
用于模拟和形式属性验证的内聚覆盖管理
作者:
Hazra
;
A.
;
Banerjee
;
A.
;
Mitra
;
S.
;
Dasgupta
;
P.
;
Chakrabarti
;
P.P.
;
Mohan
;
C.R.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
formal verification;
ARM AMBA pre-silicon verification plan;
cohesive coverage management;
formal property verification;
pre-silicon validation;
test plan language;
Coverage;
Design for Test;
Formal Property Verification;
Simulation;
Test;
Test Plan;
Verification;
56.
A Real Case of Significant Scan Test Cost Reduction
机译:
大幅降低扫描测试成本的真实案例
作者:
Sha
;
S.
;
Swanson
;
B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
integrated circuit design;
integrated circuit testing;
nanoelectronics;
DFT techniques;
clocking capabilities;
data channels;
integrated circuits;
nanometer technologies;
scan test cost reduction;
scan-based ATPG;
scan test;
test compression;
test cost;
57.
A Network Based Functional Verification Method of IEEE 1394a PHY Core
机译:
基于网络的IEEE 1394a PHY核心功能验证方法
作者:
Colin Yu Lin
;
Song Cao
;
Junshe An
;
Fei Han
;
Qifei Fan
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
IEEE standards;
formal verification;
peripheral interfaces;
protocols;
IEEE 1394a PHY core;
communication network designs;
coverage reaching;
design verification;
network based functional verification method;
network topology;
processors verification;
very complex;
58.
Uncriticality-Directed Low-Power Instruction Scheduling
机译:
面向非关键性的低功耗指令调度
作者:
Watanabe
;
S.
;
Sato
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
embedded systems;
low-power electronics;
microprocessor chips;
scheduling;
Intelligent mobile information devices;
energy consumption;
high-performance processors;
power-efficient units;
power-hungry units;
uncriticality-directed low-power instruction scheduling;
59.
A Novel System on Chip (SoC) Test Solution
机译:
新型片上系统(SoC)测试解决方案
作者:
Higgins
;
M.
;
MacNamee
;
C.
;
Mullane
;
B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
IEEE standards;
integrated circuit testing;
system-on-chip;
IEEE 1149.1 state machine;
IEEE 1500 standard;
IEEE P1687 standard;
SoC testing;
system on chip;
test access mechanism;
test controller architecture;
IEEE 1500;
IEEE P1687;
System Bus Reuse;
TAM;
Test Control;
60.
SeReCon: A Secure Dynamic Partial Reconfiguration Controller
机译:
SeReCon:安全的动态部分重配置控制器
作者:
Kepa
;
K.
;
Morgan
;
F.
;
Kosciuszkiewicz
;
K.
;
Surmacz
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
field programmable gate arrays;
logic design;
security of data;
FPGA;
IP design;
intellectual property protection;
reconfigurable computing;
secure dynamic partial reconfiguration controller;
secure runtime management;
security threat;
Dynamic Reconfiguration;
FPGA;
61.
Memory Power Modeling - A Novel Approach
机译:
内存功率建模-一种新颖的方法
作者:
Gupte
;
A.
;
Sharma
;
M.
;
Varshney
;
G.
;
Holla
;
L.
;
Rana
;
P.
;
Udayakumar
;
H.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
embedded systems;
industrial property;
integrated circuit design;
integrated memory circuits;
logic design;
low-power electronics;
system-on-chip;
IC power consumption;
accurate power estimation models;
complex IP;
dummy logic wrapper;
embedded memories;
low power c;
62.
Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory
机译:
使用博弈论的MP-SoC上温度感知的分布式运行时优化
作者:
Puschini
;
D.
;
Clermidy
;
F.
;
Benoit
;
P.
;
Sassatelli
;
G.
;
Torres
;
L.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
game theory;
system-on-chip;
MP-SoC;
dynamic voltage-frequency scaling;
embedded systems;
fully distributed scheme;
game theory;
processing elements;
run-time algorithm;
temperature-aware distributed run-time optimization;
DVFS;
Game Theory;
MP-SoC;
Optimization;
Run-;
63.
Compensating Algorithmic-Loop Performance Degradation in Asynchronous Circuits Using Hardware Multi-threading
机译:
使用硬件多线程补偿异步电路中的算法环路性能下降
作者:
Najibi
;
M.
;
Pedram
;
H.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
asynchronous circuits;
multi-threading;
program control structures;
algorithmic loop dependence;
algorithmic loop performance degradation;
asynchronous circuits;
hardware multithreading;
Asynchronous Circuits;
Hardware Multi-Threading;
Performance Optimization;
64.
A Closed-Loop Architecture with Digital Output for Convective Accelerometers
机译:
对流加速度计的数字输出闭环架构
作者:
Leman
;
O.
;
Latorre
;
L.
;
Mailly
;
F.
;
Nouet
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
accelerometers;
closed loop systems;
computerised instrumentation;
convection;
sigma-delta modulation;
closed-loop architecture;
digital output;
quantization noise shaping;
sensing cell design;
thermal convective accelerometers;
thermal sigma-delta modulation prin;
65.
Spintronic Device Based Non-volatile Low Standby Power SRAM
机译:
基于Spintronic器件的非易失性低待机功耗SRAM
作者:
Weisheng Zhao
;
Belhaire
;
E.
;
Chappert
;
C.
;
Mazoyer
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS memory circuits;
SRAM chips;
low-power electronics;
magnetic storage;
magnetic tunnelling;
magnetoelectronics;
CMOS;
magnetic tunnel junction;
microprocessor;
nonvolatile low standby power SRAM;
self-checkpointing processor;
spintronic device;
MTJ;
NVSRAM;
Spintr;
66.
BTB Access Filtering: A Low Energy and High Performance Design
机译:
BTB访问过滤:低能耗和高性能设计
作者:
Shuai Wang
;
Jie Hu
;
Ziavras
;
S.G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
computer architecture;
logic design;
microprocessor chips;
network synthesis;
BTB access filtering;
SPEC2000 benchmark;
branch predictors;
branch target buffer;
deeply-pipelined designs;
instruction-level parallelism exploitation;
superscalar processors;
BTB access;
67.
Improving Bandwidth while Managing Phase Noise and Spurs in Fractional-N PLL
机译:
在分数N PLL中管理相位噪声和杂散的同时改善带宽
作者:
Xiao Pu
;
Thomsen
;
A.
;
Abraham
;
J.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
phase locked loops;
phase noise;
bandwidth enhancement;
fractional-N PLL;
jitter;
loop bandwidth;
phase noise;
wideband fractional-N synthesizer;
wireless communication;
PLL;
bandwidth;
fractional-N;
frequency synthesizer;
phase noise;
spurs;
68.
Systematic HDL Design of a S-? Fractional-N Phase-Locked Loop for Wireless Applications
机译:
S-?的系统HDL设计无线应用的小数N锁相环
作者:
El Oualkadi
;
A.
;
Flandre
;
D.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
hardware description languages;
phase locked loops;
radiocommunication;
transistors;
Sigma-Delta fractional-N phase-locked loop;
VHDL-AMS;
behavioral modeling;
systematic HDL design;
transistor-level simulations;
wireless applications;
Fractional-N;
Frequency synth;
69.
A Novel Low-Power Clock Skew Compensation Circuit
机译:
新型低功耗时钟偏斜补偿电路
作者:
Rong Ji
;
Liang Chen
;
Gang Luo
;
Xianjun Zeng
;
Junfeng Zhang
;
Yingjie Feng
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
delay circuits;
delay lock loops;
synchronisation;
clock deskew circuit;
clock frequencies;
coarse delay line;
data transfers;
delay-locked loop deskewing;
low-power clock skew compensation circuit;
periodic synchronization signal;
skew reduction technique;
synchro;
70.
CMOS Control Enabled Single-Type FET NASIC
机译:
CMOS控制使能型FET NASIC
作者:
Narayanan
;
P.
;
Leuchtenburg
;
M.
;
Teng Wang
;
Moritz
;
C.A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
field effect transistors;
nanowires;
CMOS-nanoscale circuit;
FET NASIC;
circuit density;
field effect transistor;
microprocessor design;
NASIC;
Nano-architectures;
Nanocircuits;
Semiconductor Nanowires;
71.
Impact of Technology Scaling on Digital Subthreshold Circuits
机译:
技术扩展对数字门限电路的影响
作者:
Bol
;
D.
;
Ambroise
;
R.
;
Flandre
;
D.
;
Legat
;
J.-D.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit noise;
digital circuits;
low-power electronics;
RCA multiplier;
digital subthreshold circuits;
energy efficiency;
nonminimum channel length;
static energy consumption;
static noise margin;
technology scaling;
CMOS digital circuits;
robustness;
subthreshold l;
72.
High Speed Ultra Low Voltage CMOS inverter
机译:
高速超低压CMOS反相器
作者:
Berg
;
Y.
;
Mirmotahari
;
O.
;
Lomsdalen
;
J.G.
;
Aunet
;
S.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
high-speed integrated circuits;
invertors;
low-power electronics;
CMOS process;
Spectre simulator;
ULV;
effective threshold voltage;
high speed ultra low voltage CMOS inverter;
offsets voltages;
semi-floating-gate nodes;
size 90 nm;
ultra l;
73.
Process Algebra Based SoC Test Scheduling for Test Time Minimization
机译:
基于过程代数的SoC测试计划,可最大程度地缩短测试时间
作者:
Jingbo Shao
;
Guangsheng Ma
;
Zhi Yang
;
Ruixue Zhang
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
concurrency control;
integrated circuit testing;
parallel processing;
process algebra;
resource allocation;
scheduling;
system-on-chip;
SoC test scheduling;
concurrent processing;
optimal SoC test automation;
parallel test action;
power consumption;
process algebra;
74.
Improving the Test of NoC-Based SoCs with Help of Compression Schemes
机译:
借助压缩方案改善基于NoC的SoC的测试
作者:
Dalmasso
;
J.
;
Cota
;
E.
;
Flottes
;
M.-L.
;
Rouzeyre
;
B.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit testing;
data compression;
network-on-chip;
NoC-based SoC;
compression schemes;
test interfaces;
test parallelism;
testing methods;
Network on Chip;
System on Chip Testing;
Test Data Compression;
75.
Design of Fractal Image Compression on SOC
机译:
SOC的分形图像压缩设计
作者:
Jedidi
;
A.
;
Rejeb
;
B.
;
Abid
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
data compression;
digital signal processing chips;
fractals;
hardware-software codesign;
image coding;
system-on-chip;
SOC;
TV broadcasting;
data compression;
digital data transmission;
encoding algorithm;
fractal image compression;
hardware software design;
video ap;
76.
Transforms and Quantization in the High-Throughput H.264/AVC Encoder Based on Advanced Mode Selection
机译:
基于高级模式选择的高吞吐量H.264 / AVC编码器中的变换和量化
作者:
Pastuszak
;
G.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
computational complexity;
field programmable gate arrays;
quantisation (signal);
rate distortion theory;
video coding;
FPGA Stratix II devices;
advanced mode selection;
compression efficiency;
computational complexity;
frequency 100 MHz;
high-throughput H.264-AVC;
77.
Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications
机译:
针对多标准电信应用的片上系统的通信中心建模
作者:
Ahmadinia
;
A.
;
Ahmad
;
B.
;
Arslan
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Viterbi decoding;
WiMax;
fast Fourier transforms;
integrated circuit design;
integrated circuit interconnections;
integrated circuit modelling;
reconfigurable architectures;
system-on-chip;
ARM processor;
SoC architecture;
SoC design;
WiMAX;
communication centric mo;
78.
A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation
机译:
感知电源电压变化的低功耗缓冲树构建算法
作者:
Yibo Wang
;
Yici Cai
;
Xianlong Hong
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
circuit optimisation;
integrated circuit design;
low-power electronics;
network routing;
simulated annealing;
trees (mathematics);
IC design;
buffered routing trees;
low-power buffered tree construction algorithm;
power dissipation problem;
supply voltage variatio;
79.
Petri Net Based Rapid Prototyping of Digital Complex System
机译:
基于Petri网的数字复杂系统快速原型设计。
作者:
Andreu
;
D.
;
Souquet
;
G.
;
Gil
;
T.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
Petri nets;
hardware description languages;
programmable logic devices;
software prototyping;
VHDL components;
VHDL language;
automatic translation;
digital complex system;
interpreted generalized petri nets;
power consumption;
programmable logic device;
rapid prot;
80.
A Versatile Linear Insertion Sorter Based on a FIFO Scheme
机译:
基于FIFO方案的多功能线性插入分类器。
作者:
Perez-Andrade
;
R.
;
Cumplido
;
R.
;
Del Campo
;
F.M.
;
Feregrino-Uribe
;
C.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
coprocessors;
digital signal processing chips;
field programmable gate arrays;
filtering theory;
sorting;
statistical analysis;
FIFO;
FPGA;
coprocessor;
field programmable gate array;
first in first out scheme;
identical processing element;
linear insertion sorter;
o;
81.
A Programmable Frequency Divider in 0.18 um(micro-meter) CMOS Library
机译:
0.18 um(微米)CMOS库中的可编程分频器
作者:
Qingsheng Hu
;
Hua-An Zhao
;
Chen Liu
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS logic circuits;
digital video broadcasting;
frequency dividers;
frequency synthesizers;
thyristors;
CMOS library;
PLL frequency synthesizer;
back-end information;
custom wire-load model;
digital video broadcasting-terrestrial;
dual-modulus prescaler;
front-end;
82.
Reliability of n-Bit Nanotechnology Adder
机译:
n位纳米技术加法器的可靠性
作者:
Hanninen
;
I.
;
Takala
;
J.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
adders;
carry logic;
failure analysis;
integrated circuit reliability;
logic design;
matrix decomposition;
nanoelectronics;
quantum dots;
circuit technology;
design for reliability;
expected failure rate;
logic design robustness;
macrolevel components;
multibit rippl;
83.
A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures
机译:
一种用于Manycore架构的系统级片上资源分配新方法
作者:
Theocharides
;
T.
;
Michael
;
M.K.
;
Polycarpou
;
M.
;
Dingankar
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
computer architecture;
resource allocation;
manycore architectures;
off-chip multiprocessor architectures;
on-chip processor;
resource allocation method;
system-level bidding-based algorithms;
Chip Multiprocessors;
Manycore Architectures;
Networks on Chip;
Resourc;
84.
MPI-Based Adaptive Task Migration Support on the HS-Scale System
机译:
HS-Scale系统上基于MPI的自适应任务迁移支持
作者:
Saint-Jean
;
N.
;
Benoit
;
P.
;
Sassatelli
;
G.
;
Torres
;
L.
;
Robert
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
application program interfaces;
message passing;
multiprocessing systems;
program compilers;
system monitoring;
system-on-chip;
HS-Scale system;
MJPEG;
MPI-based adaptive task migration support;
VLSI system;
architecture scalability;
dynamic behavior monitoring;
hom;
85.
Low Power High Performance Digitally Assisted Pipelined ADC
机译:
低功耗高性能数字辅助流水线ADC
作者:
Jalali Farahani
;
B.
;
Meruva
;
A.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
analogue-digital conversion;
calibration;
low-power electronics;
analog circuit imperfection;
calibration engine;
capacitor mismatch;
digital calibration circuit;
digital calibration unit;
digitally assisted pipelined ADC;
multibit internal DAC;
pipeline analog to;
86.
Design of Robust and High-Performance 1-Bit CMOS Full Adder for Nanometer Design
机译:
用于纳米设计的稳健而高性能的1位CMOS全加法器设计
作者:
Kavehei
;
O.
;
Azghadi
;
M.R.
;
Navi
;
K.
;
Mirbaha
;
A.-P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
adders;
logic design;
1-bit CMOS full adder;
CMOS logic design;
HSPICE;
nanometer design;
nanometer scale transistors;
transistor scaling;
voltage scaling;
CMOS;
Full Adder;
High-Performance;
Robust;
VLSI;
87.
A Novel and Scalable RSA Cryptosystem Based on 32-Bit Modular Multiplier
机译:
基于32位模乘器的新型可扩展RSA密码系统
作者:
Jin-Hua Hong
;
Wen-Jie Li
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
logic design;
microprocessor chips;
multiplying circuits;
public key cryptography;
32-bit modular multiplier;
512-bit modular exponentiation;
critical path delay;
scalable RSA cryptosystem chip design;
Montgomery''s algorithm;
RSA;
modular multiplier;
public-key cr;
88.
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement
机译:
同时进行门大小调整和偏斜调度以提高统计产量
作者:
Mirsaeedi
;
M.
;
Zamani
;
M.S.
;
Saeedi
;
M.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
logic gates;
scheduling;
statistical analysis;
timing circuits;
clock skew scheduling;
combinational-sequential optimization;
simultaneous gate sizing;
statistical yield improvement;
yield loss;
89.
Raising the Level of Abstraction for the Timing Verification of System-on-Chips
机译:
提高芯片级系统时序验证的抽象水平
作者:
Chakraborty
;
R.
;
Chowdhury
;
D.R.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
formal verification;
system-on-chip;
timing;
SDF file;
SoC;
system-level timing verification method;
system-on-chip;
timing criteria;
system-on-chip;
timing verification;
90.
In Situ Design of Register Operations
机译:
寄存器操作的原位设计
作者:
Burckel
;
S.
;
Gioan
;
E.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
logic design;
electronic circuits design;
program design;
register operations design;
boolean mapping;
circuit design;
memory optimization;
processor optimization;
program design;
register operation;
91.
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
机译:
标准单元和门阵列的热感知放置:研究和观察
作者:
Ghosal
;
P.
;
Samanta
;
T.
;
Rahaman
;
H.
;
Dasgupta
;
P.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
VLSI;
cells (electric);
integrated circuit reliability;
logic arrays;
low-power electronics;
thermal management (packaging);
chip reliability;
dissipated heat;
gate arrays;
high-performance VLSI circuits;
on-chip power densities;
standard cells;
thermal-aware placem;
92.
Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques
机译:
Hermes-GLP:具有功率控制技术的片上GALS网络路由器
作者:
Pontes
;
J.
;
Moreira
;
M.
;
Soares
;
R.
;
Calazans
;
N.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
asynchronous circuits;
integrated circuit design;
logic design;
low-power electronics;
network routing;
network-on-chip;
GALS system design;
Hermes-GLP GALS network-on-chip router;
NoC communication architectures;
globally asynchronous locally synchronous system;
93.
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
机译:
通过温度感知配置选择提高可配置缓存的能效
作者:
Noori
;
H.
;
Goudarzi
;
M.
;
Inoue
;
K.
;
Murakami
;
K.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
CMOS integrated circuits;
cache storage;
leakage currents;
low-power electronics;
CMOS designs;
configurable caches;
energy efficiency;
instruction cache;
leakage current;
temperature-aware configuration selection;
total power dissipation;
Configurable Cache;
Low En;
94.
SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip
机译:
SDVM ^ R:用于基于FPGA的多核片上系统的可扩展固件
作者:
Hofmann
;
A.
;
Waldschmidt
;
K.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
field programmable gate arrays;
firmware;
system-on-chip;
virtual machines;
FPGA-based multi-core systems-on-chip;
SDVM;
dynamic reconfiguration;
parallel computing;
scalable dataflow-driven virtual machine;
transparent runtime-reconfiguration;
virtualization laye;
95.
Testing Skew and Logic Faults in SoC Interconnects
机译:
测试SoC互连中的偏斜和逻辑故障
作者:
Hernandez
;
N.
;
Champac
;
V.
会议名称:
《Quality Software (QSIC), 2008 Eighth International Conference on; Montpellier,France》
关键词:
automatic test equipment;
built-in self test;
system-on-chip;
BIST;
SoC interconnects;
automatic test equipment;
built-in self test;
logic faults;
signal integrity verification;
skew testing;
system-on-chip;
time critical signals;
delay;
logic fault;
overshoot;
skew;
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