Resynthesis of combinational logic circuits for improved path delayfault testability using comparison units

摘要

We propose a resynthesis method that modifies a given circuit tonreduce the number of paths in the circuit and thus improve its pathndelay fault testability. The resynthesis procedure is based on replacingnsubcircuits of the given circuit by structures called comparison units.nA subcircuit can be replaced by a comparison unit if it implements anfunction belonging to the class of comparison functions defined here.nComparison units are fully testable for stuck-at faults and for pathndelay faults. In addition, they have small numbers of paths and gates.nThese properties make them effective building blocks for resynthesis tonimprove the path delay fault testability of a circuit. Experimentalnresults demonstrate considerable reductions in the number of paths andnincreased path delay fault testability. These are achieved withoutnincreasing the number of gates, or the number of gates along the longestnpath in the circuit. The random pattern testability for stuck-at faultsnremains unchanged