Design of Minimum Fault Test Schedules and Testable Realizations for Combinational Logic Circuits

摘要

Techniques for deriving the minimum length tests are developed for irredundant combinational circuits that contain single faults. The development is based on the Boolean difference function. The Boolean difference function is expanded to form two analytical expressions that can be used to calculate the tests for any stuck-at-zero and stuck-at-one fault within the circuit. A map method, that allows one to choose a minimum length test directly, is then developed from the analytical expressions. A tabular method, that is amenable to automated programming techniques, is also developed. Both the map and tabular techniques facilitate the derivation of a minimum length test, for a circuit, directly from the Boolean expression that describes it. The effect of circuit redundancy on the test length is also investigated. Bounds are established for the test length required to completely test irredundant logic circuits for single faults. The bounds can also be calculated directly from the Boolean description of the circuit in question. (Author)