A technological and electrical study of self-aligned charge-trap split-gate memory devices

摘要

In this work, self-aligned charge trap split-gate devices with memory gate lengths down to 16 nm and select gate lengths down to 30 nm are fabricated and studied. Main technological issues are addressed. We present the impact of charge-trap layer (SiN or Si-nc), of memory gate length and also of spacer memory shape on electrical results (programming window). We show functionality of ultra-scaled devices, with good programming and erasing performances.