Optimized trench MOSFET technologies for power devices

摘要

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V/sub DB/=55 V (R/sub sp/=0.2 m Omega -cm/sup 2/, k/sub D/=5.7 Omega -pF) and V/sub DB/=35 V (R/sub sp/=0.15 m Omega -cm/sup 2/, k/sub D/=4.3 Omega -PF) were developed where V/sub DB/ is the drain-source avalanche breakdown voltage, R/sub sp/ is the specific on-state resistance, and k/sub D/=R/sub sp/C/sub sp/ is the input device technology factor where C/sub sp/ is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model.