P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

摘要

A Flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) $V_{rm th}$ window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled Flash memory cells. Both device simulation and experimental verification are presented.