Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors Under Synchronized Voltage Stress

摘要

Device degradation of n-type metal-induced laterally crystallized polycrystalline silicon thin-film transistors is systematically investigated under synchronized $V_{g}$ and $V_{d}$ pulse stresses. on-state degradation is dominated by a pulse duty-time-related self-heating (SH) mechanism for low-frequency stresses whereas by a pulse transient time-related dynamic hot carrier (HC) mechanism for high-frequency stresses. off-state degradation is dominated by the dynamic HC effect, irrespective of stress frequency. It is first observed that such dynamic HC degradation is independent of the pulse falling time $(t_{f})$ but dependent on the rising time $(t_{r})$. During $t_{r}$, HCs are generated in the drain depletion region by a high transient coupling electric field arising from $V_{g}$ switching. However, during $t_{f}$, the HC effect is screened by SH that caused high temperature rise. Device saturation is confirmed to play a key role in dynamic HC degradation under synchronized stresses. The proposed degradation model is verified by comparing it with various stress test results.