Impact of Charge-Trap Layer Conductivity Control on Device Performances of Top-Gate Memory Thin-Film Transistors Using IGZO Channel and ZnO Charge-Trap Layer

摘要

A top-gate-structured charge-trap-type memory thin-film transistors (CTM-TFTs) using In-Ga–Zn-O (IGZO) channel and ZnO charge-trap layers were proposed to investigate effects of conductivity modulation for charge-trap layers on the memory performances. The electrical conductivity of ZnO charge-trap layers were controlled by varying the deposition temperatures to 100 °C (CTM1), 150 °C (CTM2), and 200 °C (CTM3) during the atomic layer deposition process and this strategy was well confirmed in the controlled devices using the conductivity-modulated ZnO channel layers. The IGZO TFT without charge-trap layer was also evaluated to have excellent device characteristics thanks to the high-quality interface between IGZO and Al₂O₃ tunneling layer. The CTM1 and CMT2 exhibited a wide memory window (MW), sufficiently high program speed, and strong endurance properties. However, these promising memory behaviors could not be obtained for the CTM3 owing to its highly conductive charge-trap layer. For the evaluation of retention properties, there were big difference between the CTM1 and CTM2. Consequently, the CTM1 exhibited best memory performances. The MW and the memory margin in programmed current ( (I_{mathrm{{scriptstyle ON}}}/{mathrm{{scriptstyle OFF}}}) ) were estimated to be 17.1 V, and (1.3times 10^{8}) , respectively. The (I_{mathrm{{scriptstyle ON}}}/{mathrm{{scriptstyle OFF}}}) was obtained to be (2.6times ) (10^{6}) and (1.8times 10^{3}) after the (10^{4}) times cyclic operations and after the retention test for (10^{4}) s, respectively.