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Simulation and Experimental Study of the Warpage of Fan-Out Wafer-Level Packaging: The Effect of the Manufacturing Process and Optimal Design

机译:扇形晶圆级包装翘曲的模拟和实验研究:制造工艺和优化设计的影响

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In this paper, warpage of fan-out wafer-level packaging (FOWLP) throughout the manufacturing process is investigated to minimize the warpage. FOWLP technology has the advantages of low cost, small form factor, efficient electrical performance, and increased input-output counts. The main benefit of fan-out packaging is that it utilizes the redistribution layer to interconnect the die and solder joints instead of using the substrate. However, warpage control is still a critical issue in the wafer molding process. Warpage is induced by the coefficient of thermal expansion mismatch between the die and the molding compound. Throughout the manufacturing process, the warpage of each step was recorded by utilizing the continuity simulation. The debonding process, grinding process, and annealing process at room temperature were analyzed via the simulation results and the experimental results. To simulate the wafer molding process in a continuous manner, the element birth and death technique was employed using finite-element modeling. This method can be used to reactive and deactivate elements when the material is added to or removed from the system. The results of the measurement and simulation were highly similar, with a difference of less than 10%. However, the results differed considerably when the wafer thickness was small. The results revealed a gap between the experimental testing and simulation modeling. Because of the wafer stiffness, the wafer is too thin to support the gravity force in the experimental testing process. Therefore, it is important to determine the calibration factor to decrease the gap between experimental testing and simulation modeling. In addition, it is crucial to determine the key factor controlling the warpage behavior and to minimize the warpage by evaluating the die arrangement and the die size in this paper. Overall, the simulation modeling represents a feasible approach for predicting the warpage during the manufacturing process.
机译:在本文中,研究了扇形晶圆级封装(FOWLP)在整个制造过程中的翘曲,以最大程度地减少翘曲。 FOWLP技术具有成本低,外形小巧,电性能高以及输入输出数量增加的优点。扇出封装的主要好处是它利用重新分布层来互连管芯和焊点,而不是使用基板。然而,翘曲控制仍然是晶片成型过程中的关键问题。翘曲是由模具和模塑料之间的热膨胀系数不匹配引起的。在整个制造过程中,利用连续性仿真记录了每个步骤的翘曲。通过仿真结果和实验结果分析了室温下的脱胶工艺,磨削工艺和退火工艺。为了以连续方式模拟晶片成型过程,使用了有限元建模的元素生死技术。当材料添加到系统中或从系统中删除时,此方法可用于使元素反应和停用。测量和模拟的结果高度相似,相差不到10%。然而,当晶片厚度小时,结果差异很大。结果表明,实验测试与仿真建模之间存在差距。由于晶片的刚度,晶片太薄而无法在实验测试过程中支撑重力。因此,确定校准因子以减小实验测试与仿真建模之间的差距非常重要。另外,至关重要的是确定影响翘曲行为的关键因素,并通过评估模具布置和模具尺寸来最大程度地减少翘曲。总体而言,仿真模型代表了一种预测制造过程中翘曲的可行方法。

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