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METHOD OF MANUFACTURING FAN-OUT WAFER-LEVEL PACKAGE

机译:制造扇形晶圆级包装的方法

摘要

A method of manufacturing a fan-out wafer-level package, comprising the following steps: mounting a chip (1) on an upper surface of a substrate (6) using a binder (7); performing plastic packaging formation on the upper surface of the substrate (6), wherein a plastic package material layer (2) packages the chip (1); applying a dielectric material on an upper surface of the plastic package material layer (2) to form a dielectric layer (4); removing the dielectric layer (4) at positions corresponding to input and output ends of the chip (1), then forming a lead-out line (3) and a solder ball (8) at the removal positions; performing thinning along a lower surface of the substrate (6); removing the substrate (6), binder (7) and part of the lower surface of the plastic package material layer (2) and the chip (1) such that an ultimate grinding surface is at a preset position of the chip (1) to form a packaged semi-finished product; and cutting along a cutting line between two adjacent chips on the packaged semi-finished product to form individual packaged structures from the packaged semi-finished product. The invention can greatly reduce process steps in the process of fan-out packaging and greatly reduce packaging costs while ensuring packaging reliability.
机译:一种制造扇出晶片级封装的方法,包括以下步骤:使用粘合剂(7)将芯片(1)安装在基板(6)的上表面上;在基板(6)的上表面进行塑料封装形成,其中塑料封装材料层(2)封装芯片(1);在塑料包装材料层(2)的上表面上施加介电材料以形成介电层(4);在与芯片(1)的输入和输出端相对应的位置处去除介电层(4),然后在去除位置处形成引出线(3)和焊球(8);沿基板(6)的下表面进行减薄;去除基板(6),粘合剂(7)以及塑料包装材料层(2)和芯片(1)的下表面的一部分,以使最终的研磨表面位于芯片(1)的预设位置,从而形成包装的半成品;沿着包装的半成品上的两个相邻芯片之间的切割线切割,以从包装的半成品形成单独的包装结构。本发明可以大大减少扇出包装过程中的工艺步骤,并在保证包装可靠性的同时大大降低包装成本。

著录项

  • 公开/公告号WO2017000852A1

    专利类型

  • 公开/公告日2017-01-05

    原文格式PDF

  • 申请/专利权人 NATIONAL CENTER FOR ADVANCED PACKAGING CO.LTD.;

    申请/专利号WO2016CN87232

  • 发明设计人 JIANG FENG;LU YUAN;

    申请日2016-06-27

  • 分类号H01L21/50;H01L21/56;H01L21/60;

  • 国家 WO

  • 入库时间 2022-08-21 13:33:14

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