首页> 外文期刊>测试科学与仪器:英文版 >Electrical Characterization of the through Via in Package-on-Package with Interposer using Parameter Extraction Method
【24h】

Electrical Characterization of the through Via in Package-on-Package with Interposer using Parameter Extraction Method

机译:使用参数提取方法通过内插器进行叠层封装中的过孔的电学表征

获取原文
获取原文并翻译 | 示例
       

摘要

正This paper describes a method to extract electrical parameters of the through via in Package-on-Package(PoP)with interposer.Using the de-embedding technique electrical parameters of the through via are extracted.With the extracted electrical parameters of the through via,the effects of via height,the distance between signal and GND vias,and anti-pad clearance on the electrical characteristics are discussed. parameter extraction;de-embedding; Package-on-Package(PoP)
机译:<正>本文介绍了一种利用中介层在PoP封装中提取通孔电参数的方法,利用去嵌入技术提取了通孔的电参数。讨论了通孔高度,通孔高度,信号与GND通孔之间的距离以及防焊盘间隙对电气特性的影响。参数提取;去嵌入;层叠包装(PoP)

著录项

获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号