SOI部分耗尽SiGeHBT集电结空间电荷区模型

摘要

SiGe heterojunction bipolar transistor （HBT） on thin film SOI has been successfully integrated with SOI CMOS by ＂folded collector＂. This paper deals with the collector of ＂partially depleted transistor＂ according to the thin film vertical SiGe HBT structure. A simplified circuit model including vertical and horizontal resistors and depletion capacitance is presented for the first time, and the model of the collector for field, voltage, and depletion width is systematically established. The model is analyzed with reasonable parameters. The results indicate that the space charge region consists of intrinsic junction depletion and M0S capacitance depletion, that the width of the space charge region increases with doping concentration of the collector, larger reverse junction voltage, and smaller substrate voltage, and that the region features a vertical expansion followed by a lateral expansion. This space charge region model of collector provides a valuable reference to the SiGe ram-wave BiCMOS circuit design and simulation on thin film SOI.%SOI上的薄膜异质SiGe晶体管通过采用“折叠”集电极，已成功实现SOI上CMOS与HBT的兼容．本文结合SOI薄膜上的纵向SiGeHBT结构模型，提出了包含纵向、横向欧姆电阻和耗尽电容的“部分耗尽（partially depleted）晶体管”集电区简化电路模型．基于器件物理及实际考虑，系统建立了外延集电层电场、电势、耗尽宽度模型，并根据该模型对不同器件结构参数进行分析．结果表明，空间电荷区表现为本征集电结耗尽与MOS电容耗尽，空间电荷区宽度随集电结掺杂浓度减小而增大，随集电结反偏电压提高而增大，随衬底