Development of a production worthy CMP process at the 0.13 μm technology node with copper/SOD low-k (k < 2.7) interconnections are reported. The major challenges including low-k material, growing number in interconnects, and CMP productivity was discussed. According to new materials, architectures, and requirements, CMP process with high removal rate, high planarity, as well as high productivity was required. In this study, CMP process of delamination free integrated with SOD low-k in dual-damascene structures were developed. Copper removal rate of 1,700 nm/min and non-uniformity of 0.68 % were achieved. Criterions of planarity control were derived based on the IMD thickness and the number of wiring. Hard mask remaining was controlled within 30 nm. In addition, the productivity was greatly improved. A production worthy CMP process for copper/SOD low-k integration was fully demonstrated. Finally, the extensibility of CMP process into the sub-0.13 μm technology node is addressed.
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