Characterization of the oxide CMP process for shallow trench isolation based advanced bicmos technologies

摘要

Topography induced by buried layer formation and shallow trench isolation (STI) in advanced BiCMOS processes results in polysilicon stringer defectivity. Overpolishing during trench chemical mechanical planarization (CMP) reduces the defectivity but can also degrade device electrical characteristics. In this paper, we discuss the physical and electrical effects of CMP process for STI integration and define a CMP process window in terms of process and device. We also detail how the use of dummy active regions can impact polish uniformity and device performance.