Package reliability: How can we use ideas/methods from semiconductor reliability in package reliability?

摘要

Are the fields of fracture mechanics, rheology, etc. good enough to address issues In package reliability? No: JEDEC specs all based on DIP wirebond packages. Are we using results from these fields enough or most effectively? Not addressed. Biggest difference with wafer reliability is stressors on chip are local (E-field, temperature), which stressors in a package are mechanical stress, which is resultant of the entire package materials' CTE.