首页> 外文会议>International Conference on Electronics Packaging (Formerly IEMT/IMC Symposium) >Micro Bump Interconnections and Encapsulation Technologies on 3D Stacked LSI
【24h】

Micro Bump Interconnections and Encapsulation Technologies on 3D Stacked LSI

机译:3D堆叠式LSI上的微凸点互连和封装技术

获取原文

摘要

The substantial technologies for the 3D stacked LSI are the interconnections of the microbumps on the through-hole electrodes and the encapsulation of the narrow gaps through the layered devices. Regarding with the interconnections, the high-accurate bonding (HAB) process was achieved for the interconnections in 20μm pitch utilizing the gold bumps. The mounting accuracy was in +/-2μm. As for the advanced bonding processes at the lower temperature and the stress, the two metallurgical bonding processes were evaluated. One is the ultrasonic flip-chip bonding (UFB) process on the gold bumps and the other is the copper-bump bonding (CBB) process with the thin-metal caps. The possibility of the microbump interconnections in 20μm pitch and the basic process conditions were confirmed. Moreover, the optimized resin properties and the process control were applied to the encapsulation process for the microthin gaps less than 10μm to realize the advanced 3D LSI structure.
机译:3D堆叠LSI的实质技术是通孔电极上的微型凸点的互连以及通过分层器件的窄间隙的封装。关于互连,利用金凸点以20μm的间距实现了高精度的键合(HAB)工艺。安装精度为+/-2μm。至于在较低温度和应力下的先进键合工艺,对两种冶金键合工艺进行了评估。一种是在金凸块上进行超声倒装芯片键合(UFB)工艺,另一种是使用薄金属帽进行铜凸块键合(CBB)工艺。确认了在20μm间距内微凸点互连的可能性和基本工艺条件。此外,将优化的树脂性能和工艺控制应用于小于10μm的微小间隙的封装工艺,以实现先进的3D LSI结构。

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号