机译:基于3D芯片堆叠技术的微铜凸点互连
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan;
system in package (SIP); three-dimensional (3D) chip stacking LSI; interconnection; chip-on-chip (COC); Cu through-via (TV); Cu bump bonding (CBB); Cu-Sn; intermetallic compound (IMC); nano-indentation;
机译:键合参数对微间距Cu / Ni / SnAg微凸点微芯片芯片间互连可靠性的影响
机译:利用3D堆叠式LSI上的化学镀锡,在20毫米间距的低温下实现低温铜凸点互连
机译:利用3D堆叠式LSI上的化学镀锡,在低温下以20μm间距实现Cu凸点互连
机译:基于Cu-Sn微凸点结合和TSV互连技术的3D DRAM堆叠的新颖设计和可靠性评估
机译:3D堆叠芯片新兴技术的热感知优化
机译:晶圆级底部填充对热循环测试过程中超薄芯片堆叠式3D-IC组件微凸点可靠性的影响
机译:用焊接铜柱凸块的外围倒装芯片互连的微结构观察和可靠性行为