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Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

机译：用焊接铜柱凸块的外围倒装芯片互连的微结构观察和可靠性行为

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Yasumitsu Orii; Kazushige Toriyama; Sayuri Kohara; Hirokazu Noma; Keishi Okamoto; Daisuke Toyoshima; Keisuke Uenishi;
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年度 2011
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1. Thermal fatigue reliability for Cu-Pillar bump interconnection in flip chip on module and underfill effects [J] . Kwak Jae B., Chung Soonwan Soldering & Surface Mount Technology . 2015,第1期

机译：模块上倒装芯片中铜-柱状凸点互连的热疲劳可靠性和底部填充效应
2. Effects of Bonding Parameters on the Reliability of Fine-Pitch Cu/Ni/SnAg Micro-Bump Chip-to-Chip Interconnection for Three-Dimensional Chip Stacking [J] . Lu S.-T. Device and Materials Reliability, IEEE Transactions on . 2012,第2期

机译：键合参数对微间距Cu / Ni / SnAg微凸点微芯片芯片间互连可靠性的影响
3. Microstructure and reliability of hybrid interconnects by Au stud bump with Sn-0.7Cu solder for flip chip power device packaging [J] . Ji Hongjun, Wang Jiao, Li Mingyu Microelectronics & Reliability . 2016,第nova期

机译：金钉凸点与Sn-0.7Cu焊料用于倒装芯片功率器件封装的混合互连的微结构和可靠性
4. Microstructure Observation of Electromigration Behavior in Peripheral C2 Flip Chip Interconnection with Solder Capped Cu Pillar Bump [C] . Yasumitsu Orii, Kazushige Toriyama, Sayuri Kohara, International symposium on microelectronics . 2011

机译：外围C2倒装芯片互连与焊料封端的Cu支柱凸点电迁移行为的微观结构观察
5. Process development of double bump flip chip with enhanced *reliability and finite element analysis [D] . Yan, Wei. 2005

机译：具有增强的*可靠性和有限元分析的双凸点倒装芯片工艺开发
6. Defect Inspection of Flip Chip Solder Bumps Using an Ultrasonic Transducer [O] . Lei Su, Tielin Shi, Zhensong Xu, 2013

机译：使用超声波传感器检查倒装芯片焊锡凸点的缺陷
7. Peripheral Flip Chip Interconnection on Au Plated Pads using Solder-Capped Cu Pillar Bumps [O] . Hirokazu Noma, Kazushige Toriyama, Keishi Okamoto, 2011

机译：使用焊接Cu柱凸块的Au电镀焊盘上的外围倒装芯片互连
8. Analysis of the Pull Strength Behaviors of Fine-Pitch, Flip Chip Solder Interconnections Using a Au-Pt-Pd Thick Film Conductor on Low-Temperature, Co-Fired Ceramic (LTCC) Substrates [R] . Vianco, P. T., Rejent, J. A., Grazier, J. M., 2008

机译：利用au-pt-pd厚膜导体在低温共烧陶瓷（LTCC）基板上分析细间距，倒装芯片焊料互连的拉伸强度行为

Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

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