Process challenges in 0-level packaging using 100μm-thin chip capping with TSV

摘要

This paper presents the process challenges for the fabrication of 0-level packages using chip capping with throughsilicon via’s (TSV) in the capping chip/wafer. The key processing challenges addressed include the fabrication ofTSVs on capping wafers that are thinned down to 100μm and further, the Cu/Sn/Cu diffusion soldering to make anintermetallic bond for the chip capping. Integration of the TSVs on the cap wafer enables the verticalinterconnection, thus making the package with a small form factor and readiness for 3D integration. The Cu/Sn/Cubond and seal process provides a hermetic package and at the same time provide electrical connection between thecap and the device wafer. Adequate processing conditions are proposed.